Journal ArticleDOI
Power dissipation analysis and optimization of deep submicron CMOS digital circuits
R.X. Gu,Mohamed I. Elmasry +1 more
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In this paper, a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits is introduced, based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well.Abstract:
This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and /spl eta/, which reflects the drain induced barrier lowering, are also addressed.read more
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References
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Journal ArticleDOI
BSIM: Berkeley short-channel IGFET model for MOS transistors
TL;DR: The Berkeley short-channel IGFET model (BSIM) as discussed by the authors is an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design is described.
Journal ArticleDOI
Trading speed for low power by choice of supply and threshold voltages
Dake Liu,Christer Svensson +1 more
TL;DR: In this article, the tradeoff between speed and power consumption for low power consumption in CMOS VLSI by using the supply voltage and the threshold voltage as variables was investigated.
Journal ArticleDOI
Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates
TL;DR: In this article, four types of frequency dividers were fabricated on SIMOX/SOI (separation by implanted oxygen/silicon on insulator) substrates, and a novel circuit among these four circuits showed the highest operation frequency of 1.2 GHz under 1-V supply voltage, with gate lengths of 0.15 and 0.1 mu m.
Proceedings ArticleDOI
A high performance 0.25 mu m CMOS technology
Bijan Davari,W.H. Chang,M.R. Wordeman,C.S. Oh,Yuan Taur,Karen Petrillo,Dan Moy,J.J. Bucchignano,H. Ng,M. G. Rosenfield,F. J. Hohn,M. Rodriguez +11 more
TL;DR: In this article, a high performance 0.25-mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented.
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