Journal ArticleDOI
Power distribution system design methodology and capacitor selection for modern CMOS technology
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TLDR
In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.Abstract:
Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.read more
Citations
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Journal ArticleDOI
Modeling and measurement of simultaneous switching noise coupling through signal via transition
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Proceedings ArticleDOI
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
Ramon Bertran,Alper Buyuktosunoglu,Pradip Bose,Timothy J. Slegel,Gerard M. Salem,S. Carey,Richard F. Rizzolo,Thomas Strach +7 more
TL;DR: By sensing per-core noise in a multi-core chip, this paper characterize the noise propagation across the cores and opens up new opportunities for noise mitigation via workload mappings and dynamic voltage guard banding.
Proceedings ArticleDOI
Simultaneous switch noise and power plane bounce for CMOS technology
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Dissertation
High-frequency and high-performance vrm design for the next generations of processors
Kaiwei Yao,Fred C. Lee +1 more
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Journal ArticleDOI
Physics-Based Inductance Extraction for Via Arrays in Parallel Planes for Power Distribution Network Design
Jingook Kim,Liehui Ren,Jun Fan +2 more
TL;DR: In this paper, a systematic approach for inductance extraction for via arrays between two parallel planes is presented, where both self and mutual inductance values are obtained based on a cavity model.
References
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Journal ArticleDOI
Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems
Wiren D. Becker,James P. Eckhardt,R.W. Frech,George A. Katopis,Erich Klink,Michael F. McAllister,Timothy G. McNamara,Paul D. Muench,S.R. Richter,Howard H. Smith +9 more
TL;DR: In this article, the design of IBM's S/390 computer for control of mid-frequency noise is discussed, where the power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits.
Proceedings ArticleDOI
Decoupling capacitor calculations for CMOS circuits
TL;DR: Capacitor values and quantities are calculated using time and frequency domain techniques in this article, where the authors propose a method for decoupling capacitors to reduce EMC/EMI radiated noise.
Proceedings ArticleDOI
ESR and ESL of ceramic capacitor applied to decoupling applications
TL;DR: In this article, a new technique to extract ESR of decoupling capacitors is described, and a study that compares the ESL of different pad layout geometries is also presented.
Proceedings ArticleDOI
Packaging and power distribution design considerations for a Sun Microsystems desktop workstation
TL;DR: In this paper, the authors consider the resonance between chip capacitance and package inductance, and the key parameters for package power are the core power supply loop inductance and the inductances and resistance used to connect any decoupling capacitors on the package.
Proceedings ArticleDOI
Modeling and simulation of thin film decoupling capacitors
TL;DR: In this paper, thin film decoupling capacitors with a novel structure were modeled and their performance simulated and the influences of contact configurations and dielectric and metal layer thicknesses on the impedance behavior were studied.