Proposal of Ferroelectric Based Electrostatic Doping for Nanoscale Devices
TL;DR: In this paper, a ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing nonvolatile and programmable free electrons and holes for nanoscale devices.
Abstract: A ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing non-volatile and programmable free electrons and holes for nanoscale devices. We show that Fe-ED achieves non-volatility and reconfigurability via the ferroelectric film inserted into the polarity gate, producing the reconfigurable nanosheet FETs (NSFETs) without the requirement of a constant bias. Thanks to the naturally formed lightly doped drain structures and the extremely high doping concentration over $1\times 10^{21}$ cm−3 in source/drain (S/D) regions, Fe-ED NSFETs exhibit the promising potential benefits for device scaling including the improved subthreshold swing, the suppressed drain-induced barrier lowering, and the ultralow S/D region resistance. Our study suggests a promising doping strategy of Fe-ED for versatile reconfigurable nanoscale transistors and highly integrated circuits.
Citations
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TL;DR: In this article , the basic classification of reconfigurable field effect transistors is reviewed and the most important additional features that have been introduced in the last years in order to even further increase the flexibility of the devices are discussed.
Abstract: With classical scaling of CMOS transistors according to Dennard’s scaling rules running out of steam, new possibilities to increase the functionality of an integrated circuit at a given footprint are becoming more and more desirable. Among these approaches the possibility to reconfigure the functionality of a transistor on the single devices level stand out, as by such an approach the same physical circuitry is enabled to perform different tasks in different configurations of the circuit. Reconfigurable transistors that allow the reconfiguration from a p-channel to an n-channel transistor and vice versa have emerged as an important example of such devices. The basic concepts required to built such devices have been proposed more then 20 years ago and the field has continuously developed ever since. In this article first the basic classification of reconfigurable field effect transistors is reviewed an described form a new angle. In the second part the important technology enablers to construct reconfigure field effect transistors are examined. Further the historical development, starting at the proposal of the main concepts up to the current status of device and circuit development are described. The most important additional features that have been introduced in the last years in order to even further increase the flexibility of the devices are discussed. Finally the application potential of reconfigurable transistors is described placing the spotlight on hardware security and neuromorphic applications.
16 citations
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TL;DR: Ferroelectric capacitors, transistors, and tunneling junction devices used for low-power logic, high-performance memory, and neuromorphic applications are comprehensively reviewed and compared.
Abstract: Recently, transistor scaling is approaching its physical limit, hindering the further development of the computing capability. In the post-Moore era, emerging logic and storage devices have been the fundamental hardware for expanding the capability of intelligent computing. In this article, the recent progress of ferroelectric devices for intelligent computing is reviewed. The material properties and electrical characteristics of ferroelectric devices are elucidated, followed by a discussion of novel ferroelectric materials and devices that can be used for intelligent computing. Ferroelectric capacitors, transistors, and tunneling junction devices used for low-power logic, high-performance memory, and neuromorphic applications are comprehensively reviewed and compared. In addition, to provide useful guidance for developing high-performance ferroelectric-based intelligent computing systems, the key challenges for realizing ultrascaled ferroelectric devices for high-efficiency computing are discussed.
4 citations
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TL;DR: In this article , a new structural plan technique called dead channel double gate junction less FET (DG-JLFET) was proposed, which conveys benefits in all fronts of design, performance, and fabrication perspectives.
Abstract: In pursuit of lowering power densities and reducing energy efficiency constraints, execution grid of arising electronic devices are being investigated to track down alternative options for MOSFETs. Herein we present and examine a new structural plan technique for double gate junction less FET (DG - JLFET), which conveys benefits in all fronts of design, performance, and fabrication perspectives. This proposed structure is called dead channel double gate junction less FET (DC-DGJLFET). The dead channel means absence of conducting charge carriers in the mid of channel in the device due to presence of P-type layer which virtually reduces effective tSi and improve FOMs of the device. The performance metrics of DC-DGJLFET is compared with negative capacitance DC-DGJLFET designed on the same technology node. Also variability issues found in baseline transistors can be overcomed by incorporating the ferroelectric layer in the FET. The proposed NCFET is also compared with the IRDS requirements for various FOMs.
3 citations
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TL;DR: In this paper , a detailed study is presented to investigate the impact of variations in material parameters such as remnant polarization (PR), coercive field (EC) of the ferroelectric layer that constitutes the gate stack of negative capacitance reconfigurable FET (NC-R-FET).
Abstract: In the present work, a detailed study is presented to investigate the impact of variations in material parameters such as remnant polarization (PR), coercive field (EC) of the ferroelectric layer that constitutes the gate stack of negative capacitance–reconfigurable–FET (NC-R-FET). The analysis is carried over a broad temperature range to extensively investigate the impact of these variations on device performance at elevated temperatures as well. A dual-gate NC-R-FET can result in significant improvement in terms of enhanced drive current along with super steep switching characteristics. However, any unintended variation caused in ferroelectric (FE) parameters can significantly affect device performance such as decrease in gain, degradation in subthreshold swing and current drivability and this scenario can be particularly critical if device operation becomes hysteretic. Thus, in the present work, the influence of these unintended variations on the device performance of NC-R-FET is exhaustively studied over a broad temperature range.
3 citations
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TL;DR: In this article , an electrically programmable, multi-level non-volatile photonics memory cell, which can be fabricated by standard complementary metaloxide-semiconductor (CMOS) compatible processes, is proposed.
Abstract: Non-volatile multilevel optical memory is an urgent needed artificial component in neuromorphic computing. In this paper, based on ferroelectric based electrostatic doping (Fe-ED) and optical readout due to plasma dispersion effect, we propose an electrically programmable, multi-level non-volatile photonics memory cell, which can be fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. Hf0.5Zr0.5O2 (HZO) film is chosen as the ferroelectric ED layer and combines with polysilicon layers for an enhanced amplitude modulation between the carrier accumulation and the confined optical field. Insertion loss below 0.4 dB in erasing state and the maximum recording depth of 9.8 dB are obtained, meanwhile maintaining an extremely low dynamic energy consumption as 1.0-8.4 pJ/level. Those features make this memory a promising candidate for artificial optical synapse in neuromorphic photonics and parallel computing.
3 citations
References
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Book•
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01 Jul 2000
TL;DR: The Plan for This Book as mentioned in this paper is a collection of key ideas, references, and problems related to semiconductor manufacturing, including the history, development and basic concepts, manufacturing methods and equipment, measurement methods, models and simulation, limits and future trends in technologies and models.
Abstract: (NOTE: Chapters 3-11 include an Introduction, Historical Development and Basic Concepts, Manufacturing Methods and Equipment, Measurement Methods, Models and Simulation, Limits and Future Trends in Technologies and Models, Summary of Key Ideas, References, and Problems.) 1. Introduction and Historical Perspective. Introduction. Integrated Circuits and the Planar Process-Key Inventions That Made It All Possible. Semiconductors. Semiconductor Devices. Semiconductor Circuit Families. Modern Scientific Discovery-Experiments, Theory and Computer Simulation. The Plan for This Book. 2. Modern CMOS Technology. CMOS Process Flow. 3. Crystal Growth, Wafer Fabrication and Basic Properties of Silicon Wafers. 4. Semiconductor Manufacturing- Clean Rooms, Wafer Cleaning and Gettering. 5. Lithography. 6. Thermal Oxidation and the Si/SiO2 Interface. 7. Dopant Diffusion. 8. Ion Implantation. 9. Thin Film Deposition. 10. Etching. 11. Backend Technology.
473 citations
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05 Jun 2017
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Abstract: In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.
291 citations
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TL;DR: This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility.
Abstract: Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce s...
267 citations
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TL;DR: In this article, two independent gate-all-around electrodes and vertically stacked SiNW channels are used to enable dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device.
Abstract: We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.
209 citations
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TL;DR: In this paper, the ability to engineer ferroelectricity in HfO2 thin films, manufacturable and highly scaled MFM capacitors and MFIS-FETs can be implemented into a CMOS-environment.
Abstract: With the ability to engineer ferroelectricity in HfO2 thin films, manufacturable and highly scaled MFM capacitors and MFIS-FETs can be implemented into a CMOS-environment. NVM properties of the resulting devices are discussed and contrasted to existing perovskite based FRAM.
202 citations
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