Journal ArticleDOI
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,Daniel Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
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TLDR
In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.Abstract:Â
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.read more
Citations
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Proceedings ArticleDOI
Read stability and write ability analysis of dual -Vt configurations of a single cell of an SRAM array effect of process-induced intra-die Vt variations
S. Mamatha,M.B. Srinivas +1 more
TL;DR: In this paper, the effects of process induced intra-die threshold voltage Vt variations in 11 different dual-Vt cell combinations are evaluated and compared with the help of power noise margins which are obtained by finding the product of mean of voltage noise margins and mean of current noise margins.
Journal ArticleDOI
Area efficient diode and on transistor inter-changeable power gating scheme with trim options for SRAM design in nano-complementary metal oxide semiconductor technology
TL;DR: Sector-based power gating is presented which enables leakage savings while memory is in the active mode and the area overhead of the presented scheme is 8% when applied to SRAM bank array split into sectors.
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era The authors present an overview of various sources of process variations and reliability degradation mechanisms and related information to maintain performance envelope and yield as silicon devices enter the deeper regions of nanometer scaling.
Swaroop Ghosh,Kaushik Roy +1 more
TL;DR: The emerging paradigm of variation-tolerant adaptive design for both logic and memories is discussed and circuit and microarchitectural techniques to perform reliable computations in an unreliable environment are presented.
Patent
Inhibiting address transitions in unselected memory banks of solid state memory circuits
Lawrence T. Clark,Giby Samson +1 more
TL;DR: In this paper, address gating circuitry is used to provide a set of gated address signals to decode circuitry for each memory bank, such that the gated addresses associated with unselected memory banks are prevented from transitioning.
Proceedings ArticleDOI
Low power with high stability 12T MTCMOS based SRAM cell for write operation
TL;DR: The proposed SRAM cell dissipates less power at different supply voltages, bit line capacitance and better stability at different pull-down ratios than the other SRAM models, and the stability of data retention is enhanced.
References
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Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.
Journal ArticleDOI
A single-V/sub t/ low-leakage gated-ground cache for deep submicron
Amit Agarwal,Hai Li,Kaushik Roy +2 more
TL;DR: A novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process and Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
TL;DR: In this paper, a self reverse biasing scheme was proposed to address leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each.
Proceedings ArticleDOI
Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.