Journal ArticleDOI
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,Daniel Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
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TLDR
In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.Abstract:
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.read more
Citations
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Journal ArticleDOI
A novel read decoupled 8T1M nvSRAM cell for near threshold operation
TL;DR: In this article , a new nvSRAM cell is introduced which can maintain its performance near threshold voltage and reduce power consumption up to 99.7% during write '1' operation.
Posted Content
Design and Performance Analysis Of Ultra Low Power 6T SRAM Using Adiabatic Technique
TL;DR: In this article, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly, and the authors show that average power dissipation is reduced up to 75% using adi-abatic technique and also shows the effect on static noise margin.
Proceedings ArticleDOI
Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects
TL;DR: The impact of environmental noise is analyzed in SRAM cells with weak resistive-bridge defects that may escape manufacturing test due to their dynamic behavior using SPICE simulations adopting a commercial 65nm CMOS technology library.
Journal ArticleDOI
$In~Situ$ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files
TL;DR: A technique to monitor and decelerate transistor threshold voltage degradation caused by negative bias temperature instability (NBTI) in SRAM-based register files (RFs) and generate recovery vectors that can recover a good portion of NBTI degradation and thus decelerates the degradation of data retention voltage.
Journal ArticleDOI
SNM Analysis of 6T SRAM at 32NM and 45NM Technique
Anurag Dandotiya,Amit S. Rajput +1 more
TL;DR: This paper defines the read margin to characterize the SRAM cells read stability and analyzes SNM of different modulation like cell ratio, voltage supply, word line and bit line by spice tools using BPTM Low Power model in different technologies.
References
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Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.
Journal ArticleDOI
A single-V/sub t/ low-leakage gated-ground cache for deep submicron
Amit Agarwal,Hai Li,Kaushik Roy +2 more
TL;DR: A novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process and Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
TL;DR: In this paper, a self reverse biasing scheme was proposed to address leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each.
Proceedings ArticleDOI
Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.