Journal ArticleDOI
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,Daniel Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
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TLDR
In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.Abstract:
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.read more
Citations
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Journal ArticleDOI
Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries
TL;DR: In this paper, a complete leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed, and it was shown that there is approximately 30% leakage current reduction with a few percent active area and delay increase.
Journal ArticleDOI
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$ m CMOS
TL;DR: A segmented virtual grounding architecture with extended read, write noise margin to realize a low leakage current, energy efficient SRAM module and a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation.
Proceedings ArticleDOI
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC
TL;DR: This work proposes a novel ECC scheme based on erasure coding that can extend ECC to correct and detect multiple erroneous bits at low latency, area, and power overheads and shows that EB-ECC, when combined with less than 5% row redundancy, can improve the cache access latency, power, and stability by over 40% on average.
Journal ArticleDOI
Highly robust asymmetrical 9T SRAM with trimode MTCOS technique
TL;DR: In this article, the authors used MTCMOS tech for optimizing parameters like stability static power dissipation and delay and characterized the parameters of conventional 6T, Asym8T Asym 9T SRAM cell.
Journal ArticleDOI
Supply Voltage Decision Methodology to Minimize SRAM Standby Power Under Radiation Environment
TL;DR: This work presents a methodology to decide optimal supply voltage with respect to standby power under radiation, and visualize the methodology under solar max/min galactic cosmic ray radiation environment of geosynchronous earth orbit and three error correction code (ECC) scenarios: Hamming code, double-error-correction (DEC) Bose-Chaudhuri-Hocquenghem (BCH) code, and triple- Error Correction Code (TEC) BCH code.
References
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Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.
Journal ArticleDOI
A single-V/sub t/ low-leakage gated-ground cache for deep submicron
Amit Agarwal,Hai Li,Kaushik Roy +2 more
TL;DR: A novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process and Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
TL;DR: In this paper, a self reverse biasing scheme was proposed to address leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each.
Proceedings ArticleDOI
Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.