Journal ArticleDOI
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,Daniel Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
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TLDR
In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.Abstract:
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.read more
Citations
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Proceedings ArticleDOI
A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS
Muhammad M. Khellah,Nam Sung Kim,Jason Howard,G. Ruhl,M. Sunna,Yibin Ye,J. Tschanz,Dinesh Somasekhar,Nitin Borkar,F. Hamzaoglu,Gunjan H. Pandya,A. Farhang,Kevin Zhang,Vivek De +13 more
TL;DR: An SRAM macro, implemented in a 65nm CMOS process, uses a dual supply to maximize density while enabling the use of low voltage for the processor core.
Journal ArticleDOI
Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode
TL;DR: A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode.
Patent
Non-volatile SRAM cell
TL;DR: In this paper, the authors present a non-volatile static random access memory (SRAM) system that transfers data from a pair of nonvolatile storage nodes to the pair of static storage nodes when the SRAM exits the standby mode.
Journal ArticleDOI
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories
TL;DR: The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode, which leads to higher dynamic energy consumption than the conventional approach.
Proceedings ArticleDOI
Low-leakage SRAM design with dual V/sub t/ transistors
TL;DR: Experimental results show that this technique can reduce the leakage-power dissipation of a 64Kb SRAM by more than 35% and improves the static noise margin under process variations.
References
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Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.
Journal ArticleDOI
A single-V/sub t/ low-leakage gated-ground cache for deep submicron
Amit Agarwal,Hai Li,Kaushik Roy +2 more
TL;DR: A novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process and Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
TL;DR: In this paper, a self reverse biasing scheme was proposed to address leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each.
Proceedings ArticleDOI
Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.