Journal ArticleDOI
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,Daniel Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
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TLDR
In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.Abstract:Â
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.read more
Citations
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Journal ArticleDOI
SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey
Pavankumar Bikki,P. Karuppanan +1 more
TL;DR: In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed and a classification of these approaches made based on their key design and functions is made.
Proceedings ArticleDOI
8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design
TL;DR: This article proposes a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which addsnon-volatility to the SRAM with minimum impact on the Write and Read operations, and is among the best of all reported R RAM-based NV- SRAM designs to the authors' knowledge.
Patent
SRAM cell with intrinsically high stability and low leakage
TL;DR: In this paper, a Static Random Access Memory (SRAM) cell with high stability and low leakage is provided, which includes a pair of cross-coupled inverters providing differential storage of a data bit and a read-transistor providing access to the bit stored by the SRAM cell via a gate of the read transistor.
Journal ArticleDOI
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design
Fatih Hamzaoglu,Yih Wang,Pramod Kolar,Liqiong Wei,Yong-Gee Ng,Uddalak Bhattacharya,Kevin Zhang +6 more
TL;DR: Circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes are presented.
Book ChapterDOI
Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits
Hailong Jiao,Volkan Kursun +1 more
TL;DR: In this paper, a tri-mode MTCMOS circuit with three operating modes (tri-mode, SLEEP, ACTIVE) is described for noise suppression during activation events.
References
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Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.
Journal ArticleDOI
A single-V/sub t/ low-leakage gated-ground cache for deep submicron
Amit Agarwal,Hai Li,Kaushik Roy +2 more
TL;DR: A novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process and Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
TL;DR: In this paper, a self reverse biasing scheme was proposed to address leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each.
Proceedings ArticleDOI
Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.