Journal ArticleDOI
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,Daniel Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
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TLDR
In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.Abstract:
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.read more
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Proceedings ArticleDOI
A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS
Raguram Damodaran,Timothy D. Anderson,Sanjive Agarwala,Rama Venkatasubramanian,Michael C. Gill,Dhileep Gopalakrishnan,Anthony M. Hill,Abhijeet Ashok Chachad,Dheera Balasubramanian,Naveen Bhoria,Jonathan (Son) Hung Tran,Duc Quang Bui,Mujibur Rahman,Shriram D. Moharil,Matthew D. Pierson,S. Mullinnix,Hung Ong,David Matthew Thompson,Krishna Chaithanya Gurram,Oluleye Olorode,Nuruddin Mahmood,Jose Luis Flores,Arjun Rajagopal,Soujanya Narnur,Wu Daniel,Alan Hales,Kyle Peavy,Robert Sussman +27 more
TL;DR: The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.
Journal ArticleDOI
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield
TL;DR: The results show that the proposed architecture provides a remarkable restore yield and ~154% improvement in the read static noise margin (at TT corner and stable mode) and the read delay improves by ~23% (atTT corner and high-speed mode).
Proceedings ArticleDOI
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme
TL;DR: A Bitline Amplitude Limiter capable of compensating this energy degradation in SRAM caused by VDD reduction under 0.7V is proposed and it reduces leakage automatically even during the operation.
Proceedings ArticleDOI
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
TL;DR: An error-tolerant SRAM design optimized for ultra-low standby power is presented, which effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V VDD.
Journal ArticleDOI
Review of Sense Amplifiers for Static Random Access Memory
Jiafeng Zhu,Na Bai,Jianhui Wu +2 more
TL;DR: This paper provides a systematic overview of voltage-mode, charge-transfer, current-mode SAs, and calibration-based SAs for SRAM.
References
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Proceedings ArticleDOI
Characterization of multi-bit soft error events in advanced SRAMs
TL;DR: An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi -bit errors negligible.
Journal ArticleDOI
A single-V/sub t/ low-leakage gated-ground cache for deep submicron
Amit Agarwal,Hai Li,Kaushik Roy +2 more
TL;DR: A novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process and Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
TL;DR: In this paper, a self reverse biasing scheme was proposed to address leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each.
Proceedings ArticleDOI
Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.