Showing papers on "AND gate published in 2015"

Two Halves Make a Whole

Abstract: The well-known classical constructions of garbled circuits use four ciphertexts per gate, although various methods have been proposed to reduce this cost. The best previously known methods for optimizing AND gates (two ciphertexts; Pinkas et al., ASIACRYPT 2009) and XOR gates (zero ciphertexts; Kolesnikov and Schneider, ICALP 2008) were incompatible, so most implementations used the best known method compatible with free-XOR gates (three ciphertexts; Kolesnikov and Schneider, ICALP 2008). In this work we show how to simultaneously garble AND gates using two ciphertexts and XOR gates using zero ciphertexts, resulting in smaller garbled circuits than any prior scheme. The main idea behind our construction is to break an AND gate into two half-gates — AND gates for which one party knows one input. Each half-gate can be garbled with a single ciphertext, so our construction uses two ciphertexts for each AND gate while being compatible with free-XOR gates. The price for the reduction in size is that the evaluator must perform two cryptographic operations per AND gate, rather than one as in previous schemes. We experimentally demonstrate that our garbling scheme leads to an overall decrease in time (up to 25%), bandwidth (up to 33%), and energy use (up to 20%) over several benchmark applications. We show that our construction is optimal for a large class of garbling schemes encompassing all known practical garbling techniques.

Display device and driving method thereof

Abstract: A disclosed display device includes a display panel with data lines and gate lines, the gate lines including odd-numbered gate lines and even-numbered gate lines The display device also includes a timing controller to generate a gate output enable signal, and a gate output enable signal division circuit to extract odd-numbered high logic periods of the gate output enable signal to output a first gate output enable signal and to extract even-numbered high logic periods of the gate output enable signal to output a second gate output enable signal The display device further includes a gate driver to supply a first gate pulse to an odd-numbered gate line in response to the first gate output enable signal and a second gate pulse to an even-numbered gate line in response to the second output enable signal

Realization of Boolean Logic Functionality Using Redox‐Based Memristive Devices

Abstract: Emerging resistively switching devices are thought to enable ultradense passive nanocrossbar arrays for use as random access memories (ReRAM) by the end of the decade, both for embedded and mass storage applications. Moreover, ReRAMs offer inherent logic-in-memory (LIM) capabilities due to the nonvolatility of the devices and therefore great potential to reduce the communication between memory and calculation unit by alleviating the so-called von Neumann bottleneck. A single bipolar resistive switching device is capable of performing 14 of 16 two input logic functions in the logic concept presented by Linn et al. (“CRS-logic”). In this paper, five types of selectorless devices are considered to validate this CRS-logic concept is experimentally by means of the IMP and AND logic operations. As reference device a TaO x -based ReRAM cell is considered, which is compared to three more advanced device configurations consisting either of a threshold supported resistive switch (TS-ReRAM), a complementary switching device (CS), or a complementary resistive switch (CRS). It is shown that all of these devices offer the desired LIM behavior. Moreover, the feasibility of XOR and XNOR operations using a modified logic concept is applied for both CS and CRS devices and the pros and cons are discussed.

Fast boolean logic mapped on memristor crossbar

Abstract: As the CMOS technology is gradually scaling down to inherent physical device limits, significant challenges emerge related to scalability, leakage, reliability, etc. Alternative technologies are under research for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, practically zero leakage, non-volatility, etc. This paper proposes a novel design methodology for logic circuits targeting memristor crossbars. This methodology allows the optimization of the design of logic function, and their automatic mapping on the memristor crossbar. More important, this methodology supports the execution of Boolean logic functions within constant number of steps independent of its functionality. To illustrate the potential of the proposed methodology, multi-bit adders and multipliers are explored; their incurred delay, area and energy costs are analyzed. The comparison of our approach with state-of-the-art Boolean logic circuits for memristor crossbar architecture shows significant improvement in both delay (4 to 500 x) and energy consumption (1.22 to 3.71 x). The area overhead may decrease (down to 44%) or increase (up to 17%) depending on the circuit's functionality and logic optimization level.

A spin-wave logic gate based on a width-modulated dynamic magnonic crystal

Abstract: An electric current controlled spin-wave logic gate based on a width-modulated dynamic magnonic crystal is realized. The device utilizes a spin-wave waveguide fabricated from a single-crystal Yttrium Iron Garnet film and two conducting wires attached to the film surface. Application of electric currents to the wires provides a means for dynamic control of the effective geometry of waveguide and results in a suppression of the magnonic band gap. The performance of the magnonic crystal as an AND logic gate is demonstrated.

Multi-Level Logic Gate Operation Based on Amplified Aptasensor Performance†

Abstract: Conventional electronic circuits can perform multi-level logic operations; however, this capability is rarely realized by biological logic gates. In addition, the question of how to close the gap between biomolecular computation and silicon-based electrical circuitry is still a key issue in the bioelectronics field. Here we explore a novel split aptamer-based multi-level logic gate built from INHIBIT and AND gates that performs a net XOR analysis, with electrochemical signal as output. Based on the aptamer-target interaction and a novel concept of electrochemical rectification, a relayed charge transfer occurs upon target binding between aptamer-linked redox probes and solution-phase probes, which amplifies the sensor signal and facilitates a straightforward and reliable diagnosis. This work reveals a new route for the design of bioelectronic logic circuits that can realize multi-level logic operation, which has the potential to simplify an otherwise complex diagnosis to a "yes" or "no" decision.

Modelling and analysis of modular multilevel converter for solar photovoltaic applications to improve power quality

Abstract: The design of control circuit for a solar fed cascaded multilevel inverter to reduce the number of semiconductor switches is presented in this study The design includes `binary', `trinary' and `modified multilevel connection' (MMC)-based topologies suitable for varying input sources from solar photovoltaic's (PV) In binary mode, 2 Ns+1 - 1 output voltage levels are obtained where N s is the number of individual inverters This is achieved by digital logic functions which includes counters, flip-flops and logic gates In trinary mode, 3 Ns levels are achieved by corresponding look-up table MMC intends design in both control and power circuits to provide corresponding output voltage levels by appropriate switching sequences Hence to obtain a 15-level inverter, the conventional method requires 28 switches and in binary mode 12 switches are needed In trinary mode with the same 12 switches, 27 levels can be obtained whereas in MMC only 7 switches are employed to achieve 15 levels The advantage of these three designs is in the reduction of total harmonic distortion by increasing the levels Simulations are carried out in MATLAB/Simulink and comparisons were made All the three topologies are experimentally investigated for a 3 kWp solar PV plant and power quality indices were measured

Ultrafast surface plasmon-polariton logic gates and half-adder

Abstract: In this paper, we present a plasmonic model system for the realization of ultrafast all-optical NOT, AND, OR, and XOR gate operations using linear interference effects in dielectric crossed waveguide structures. The waveguides for the surface plasmon-polaritons are produced by a simple but highly accurate microscopic lithographic process and are optimized for single mode operation at an excitation laser wavelength of 800 nm. The functionality of the presented structures is demonstrated using sub-30 fs laser pulses from a mode locked titanium:sapphire laser. Using leakage radiation microscopy we show ultrafast SPP switching and logic operations of one basic structure consisting of two crossed waveguides with an additional output waveguide along the bisecting line of the input waveguides. The individual gates are realized on a footprint of 10 µm × 20 µm. Experimental investigations are supported by finite-difference time-domain simulations, where good agreement between experimental results and numerical simulations is obtained. To exploit the high precision of the fabrication method and its huge potential for realizing functional complex plasmonic circuitry we experimentally demonstrate a half-adder structure and its operation by combining and cascading several plasmonic waveguide components and logic gate elements on an area of only 10 µm × 28 µm.

A spin-wave logic gate based on a width-modulated dynamic magnonic crystal

Abstract: An electric current controlled spin-wave logic gate based on a width-modulated dynamic magnonic crystal is realized. The device utilizes a spin-wave waveguide fabricated from a single-crystal Yttrium Iron Garnet film and two conducting wires attached to the film surface. Application of electric currents to the wires provides a means for dynamic control of the effective geometry of the waveguide and results in a suppression of the magnonic band gap. The performance of the magnonic crystal as an AND logic gate is demonstrated.

Dynamic Characterization of Parallel-Connected High-Power IGBT Modules

Abstract: In high-power converter design, insulated gate bipolar transistor (IGBT) modules are often operated in parallel to reach high output currents. Evaluating the electrical and thermal behavior of the parallel IGBTs is crucial for the design and reliable operation of converter systems. This paper investigates the static and dynamic characterization of parallel IGBTs and the influence of the electrical parameters on the IGBT behavior. Si-based IGBT power modules with voltage rating of 4.5 kV and current rating of 1 kA are used for the experimental evaluation of module parallel connections. Parallel-connected modules have been driven by several commercial IGBT gate units at various dc-link voltages and current levels and with different temperatures. The tested IGBT gate units show good current sharing performance between the two parallel modules. Other important influencing factors such as busbar design layout, stray inductance variation, and gate driving are also investigated for parallel connections of IGBT modules. Finally, the switching energy of the parallel modules is extracted for IGBTs and diodes under different conditions.

Topological computation based on direct magnetic logic communication

Abstract: Non-uniform magnetic domains with non-trivial topology, such as vortices and skyrmions, are proposed as superior state variables for nonvolatile information storage. So far, the possibility of logic operations using topological objects has not been considered. Here, we demonstrate numerically that the topology of the system plays a significant role for its dynamics, using the example of vortex-antivortex pairs in a planar ferromagnetic film. Utilising the dynamical properties and geometrical confinement, direct logic communication between the topological memory carriers is realised. This way, no additional magnetic-to-electrical conversion is required. More importantly, the information carriers can spontaneously travel up to ~300 nm, for which no spin-polarised current is required. The derived logic scheme enables topological spintronics, which can be integrated into large-scale memory and logic networks capable of complex computations.

Design and synthesis of a novel PET and ICT based 1,8-naphthalimide FRET bichromophore as a four-input Disabled-Enabled-OR logic gate

Abstract: The synthesis, sensor activity and logic behavior of a novel donor–acceptor system based on ICT and PET 1,8-naphthalimide fluorescent probes is reported. The system was configured on the “fluorophore1–receptor1–fluorophore2–spacer–receptor2” model where the two probes are integrated in a logic circuit comprising a FRET bichromophoric system with multilevel fluorescent output. The synthesized compound shows colorimetric and fluorescence signaling properties as a function of pH and in the presence of transition metal ions with emphasis on Cu2+ and Pb2+. Due to the remarkable fluorescence and absorption changes in the presence of protons, hydroxide anions, Cu2+ and Pb2+ ions the novel system executes four-input Disabled–Enabled-OR logic gate as well as two-input INHIBIT and IMPLICATON logic gates and is able to act as a three output combinatorial logic circuit with four chemical inputs. Due to the parallel action of four-input input4-Disabled-input3-Enabled-OR logic gate (Output 1) with INHIBIT (Output 2) and IMPLICATON (Output 3) gates, the system can be switched over Disable and Enable mode reversible.

Transistor aging and reliability in 14nm tri-gate technology

Abstract: This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. This technology introduces Intel's 2nd generation tri-gate transistor and the 4th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.

Active gate driver for fast switching and cross-talk suppression of SiC devices in a phase-leg configuration

Abstract: This paper presents an active gate driver for Silicon Carbide (SiC) devices to fully utilize their potentials of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control the gate voltages and gate loop impedances of both devices in a phase-leg during different switching transients. Compared to a conventional gate driver, the proposed circuit has the capability of increasing the switching speed of the phase-leg power devices, suppressing the cross-talk to below device limits. Based on CREE's 2nd generation 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this active gate driver under various operating conditions. The switching time decreases by up to 28% during turn-on and 50% during turn-off in the prototype circuit, resulting in up to 31% reduction in switching energy loss. In addition, spurious gate voltages induced by cross-talk are limited within the required range.

All-optical logic gates based on nonlinear plasmonic ring resonators.

Abstract: A nonlinear plasmonic T-shaped switch based on a square-shaped ring resonator is simulated by the finite-difference time-domain numerical method. Three optical logic gates-a NOT, with one T-shaped switch, and AND and NOR gates, each with two cascaded T-shaped switches-are proposed. The nonlinear Kerr effect is utilized to show the performance of our proposed logic gates. The values of transmission at the ON and OFF states of NOT and NOR gates are 70% and less than 0.6% of the input lightwave, respectively, while these values for the AND gate are 90% and less than 30%, respectively.

Gate Modulation of Threshold Voltage Instability in Multilayer InSe Field Effect Transistors.

Abstract: We report a modulation of threshold voltage instability of back-gated multilayer InSe FETs by gate bias stress. The performance stability of multilayer InSe FETs is affected by gate bias polar, gate bias stress time and gate bias sweep rate under ambient conditions. The on-current increases and threshold voltage shifts to negative gate bias stress direction with negative bias stress applied, which are opposite to that of positive bias stress. The intensity of gate bias stress effect is influenced by applied gate bias time and the sweep rate of gate bias stress. The behavior can be explained by the surface charge trapping model due to the adsorbing/desorbing oxygen and/or water molecules on the InSe surface. This study offers an opportunity to understand gate bias stress modulation of performance instability of back-gated multilayer InSe FETs and provides a clue for designing desirable InSe nanoelectronic and optoelectronic devices.

A Three-State Nanofluidic Field Effect Switch

Abstract: We report a three-state nanofluidic field effect switch in an asymmetrically gated device with a forward (positive), off (zero), and a reverse (negative) current state for tunable control of ionic transport by systematically controlling the gate potential. The embedded gate electrode allows for modulation of the ionic current through the 16 nm deep channels as a function of electrolyte concentration and gate electrode location for a fixed streamwise potential.

A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap

Abstract: A two-dimensional (2D) analytical gate threshold voltage model for a heterojunction silicon-on-insulator tunnel field-effect transistor structure with gate oxide overlap is developed. The infinite series method, with suitable boundary conditions, is used to solve the 2D Poisson’s equation for surface potential. The surface potential is used to develop the expression for the proposed analytical threshold voltage in closed form. Developed threshold voltage is verified for different gate length, drain voltage, oxide thickness, and gate dielectric materials against Synopsys Technology Computer-Aided Design numerical simulation results and found to predict the simulated results accurately.

A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

Abstract: A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson’s equation is solved in channel region by a method of series expansion similar to Green’s function. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this expression, analytical models of threshold voltage, subthreshold swing, and subthreshold drain current for JLDGMTs were derived. Subthreshold behavior was studied in detail by changing different device parameters and bias conditions, including doping concentration, channel thickness, gate length, gate oxide thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the 2-D simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLDGMTs and to optimize their device performance.

Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

Abstract: This paper deals with the development of a generalized model describing the device electrostatic behavior of three different double gate n-type tunnel FET (TFET) architectures, i.e., dual material gate (DMG) TFET, heterodielectric (H-D) TFET, and dual material gate heterodielectric (DMG H-D). The model is advantageous in capturing the impact of dielectric and the metal gate length variation where a comparative study among these three aforementioned device architectures has been made in terms of various electrostatic parameters, such as surface potential, energy-band profile, and electric field, incorporating the impact of interface oxide charges. Subsequently, TCAD-based digital performance investigation for all these architectures has been performed where their capacitive behavior and the transient performance has been carefully analyzed and optimized by varying the metal work function ( $M_{1}$ ) and length ( $L_{1}$ ) value for both, i.e., the dielectric material and the metal gate. Both the modeling and simulation results reveal that the proposed architecture, i.e., DMG H-D TFET, outperforms the other two architectures, i.e., DMG and H-D TFET.

Wafer-scale arrayed p-n junctions based on few-layer epitaxial GaTe

Abstract: Two-dimensional (2D) materials have attracted substantial attention in electronic and optoelectronic applications with the superior advantages of being flexible, transparent, and highly tunable. Gapless graphene exhibits ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit high sensitivity and tunable responsivity to visible light. However, the device yield and repeatability call for further improvement to achieve large-scale uniformity. Here, we report a layer-by-layer growth of wafer-scale GaTe with a high hole mobility of 28.4 cm2/(V·s) by molecular beam epitaxy. The arrayed p-n junctions were developed by growing few-layer GaTe directly on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and a high photovoltaic external quantum efficiency up to 62% at 4.8 µW under zero bias. The photocurrent reaches saturation fast enough to capture a time constant of 22 µs and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photoimages were acquired by the GaTe/Si photodiodes with reasonable contrast and spatial resolution, demonstrating the potential of integrating the 2D materials with silicon technology for novel optoelectronic devices.

Voltage-driven spintronic logic gates in graphene nanoribbons

Abstract: Electronic devices lose efficacy due to quantum effect when the line-width of gate decreases to sub-10 nm. Spintronics overcome this bottleneck and logic gates are building blocks of integrated circuits. Thus, it is essential to control electronic transport of opposite spins for designing a spintronic logic gate, and spin-selective semiconductors are natural candidates such as zigzag graphene nanoribbons (ZGNR) whose edges are ferromagnetically ordered and antiferromagnetically coupled with each other. Moreover, it is necessary to sandwich ZGNR between two ferromagnetic electrodes for making a spintronic logic gate and also necessary to apply magnetic field to change the spin orientation for modulating the spin transport. By first principle calculations, we propose a method to manipulate the spin transport in graphene nanoribbons with electric field only, instead of magnetic field. We find that metal gates with specific bias nearby edges of ZGNR build up an in-plane inhomogeneous electric field which modulates the spin transport by localizing the spin density in device. The specific manipulation of spin transport we have proposed doesn't need spin-charge conversion for output and suggests a possible base for designing spintronic integrated circuit in atomic scale.

Gate driver optimization to mitigate shoot-through in high-speed switching SiC half bridge module

Abstract: The high-speed switching of SiC MOSFET allows power converter to operate with higher frequency and lower switching loss. However, it tends to aggravate dv/dt effect due to the impact of parasitic parameters, resulting in shoot-through and high device stress in the half bridge configuration. In this study, a compact and high-speed gate driver is developed and optimized for SiC half bridge module. The impact of various circuit parameters including Miller capacitance, common source inductance, gate resistance and gate inductance is evaluated. The improved gate drivers with additional features are compared and optimized to eliminate shoot-through.

Resolving ambiguities in nanowire field-effect transistor characterization

Abstract: We have modeled InAs nanowires using finite element methods considering the actual device geometry, the semiconducting nature of the channel and surface states, providing a comprehensive picture of charge distribution and gate action. The effective electrostatic gate width and screening effects are taken into account. A pivotal aspect is that the gate coupling to the nanowire is compromised by the concurrent coupling of the gate electrode to the surface/interface states, which provide the vast majority of carriers for undoped nanowires. In conjunction with field-effect transistor (FET) measurements using two gates with distinctly dissimilar couplings, the study reveals the density of surface states that gives rise to a shallow quantum well at the surface. Both gates yield identical results for the electron concentration and mobility only at the actual surface state density. Our method remedies the flaws of conventional FET analysis and provides a straightforward alternative to intricate Hall effect measurements on nanowires.

Radio-frequency switch having dynamic body coupling

Abstract: Radio-frequency (RF) switch circuits are disclosed including at least one first field-effect transistor (FET) disposed between first and second nodes, each of the at least one first FET having a respective body and gate. The RF switch circuit may include a coupling circuit that couples the respective body and gate of the at least one first FET, the coupling circuit configured to be switchable between a resistive-coupling mode and a body-floating mode, as well as an adjustable-resistance circuit connected to either or both of the respective gate and body of the at least one FET, the adjustable-resistance circuit including a resistor in parallel with a bypass switch.