Showing papers on "Bipolar junction transistor published in 2019"

Practical Design Considerations for a Si IGBT + SiC MOSFET Hybrid Switch: Parasitic Interconnect Influences, Cost, and Current Ratio Optimization

Abstract: In this paper, a hybrid switch (HyS) consisting of a large current rated Si insulated-gate bipolar transistor (IGBT) device connected in parallel with a small current rated SiC MOSFET device (low SiC/Si current ratio below unity) is proposed for high-current high-power converters. A systematic analysis involving a parametric sweep to understand the influence and to derive a boundary line of the parasitic interconnection inductance unbalance between Si and SiC within the HyS is presented. The boundary line prescribes the selection of an appropriate gate sequence control. A comprehensive cost analysis was performed using commercial 1.2 kV devices to demonstrate the cost viability of a 1:4 or 1:6 SiC/Si current ratio HyS compared to a SiC MOSFET. An algorithm using a dynamic junction temperature prediction is presented to select an optimum SiC/Si current ratio, which ensures a reliable HyS operation. Using a design example, the possibility of reliability using a 1:6 SiC/Si HyS is studied. A 650 V Si-IGBT- and SiC-MOSFET-based HyS (1:5 SiC/Si current ratio) was successfully demonstrated in a dc–dc boost converter. Also, electromagnetic interference analysis is presented for the HyS-based converter operation.

Multifunctional van der Waals Broken-Gap Heterojunction

Abstract: The finite energy band-offset that appears between band structures of employed materials in a broken-gap heterojunction exhibits several interesting phenomena. Here, by employing a black phosphorus (BP)/rhenium disulfide (ReS2 ) heterojunction, the tunability of the BP work function (Φ BP ) with variation in flake thickness is exploited in order to demonstrate that a BP-based broken-gap heterojunction can manifest diverse current-transport characteristics such as gate tunable rectifying p-n junction diodes, Esaki diodes, backward-rectifying diodes, and nonrectifying devices as a consequence of diverse band-bending at the heterojunction. Diversity in band-bending near heterojunction is attributed to change in the Fermi level difference (Δ) between BP and ReS2 sides as a consequence of Φ BP modulation. No change in the current transport characteristics in several devices with fixed Δ also provides further evidence that current-transport is substantially impacted by band-bending at the heterojunction. Optoelectronic experiments on the Esaki diode and the p-n junction diode provide experimental evidence of band-bending diversity. Additionally, the p+ -n-p junction comprising BP (38 nm)/ReS2 /BP(5.8 nm) demonstrates multifunctionality of binary and ternary inverters as well as exhibiting the behavior of a bipolar junction transistor with common-emitter current gain up to 50.

Nanoscale electronic devices based on transition metal dichalcogenides

Abstract: Two-dimensional (2D) transition metal dichalcogenides (TMDs) have very versatile chemical, electrical and optical properties. In particular, they exhibit rich and highly tunable electronic properties, with a bandgap that spans from semi-metallic up to 2 eV depending on the crystal phase, material composition, number of layers and even external stimulus. This paper provides an overview of the electronic devices and circuits based on 2D TMDs, such as Esaki diodes, resonant tunneling diodes (RTDs), logic and RF transistors, tunneling field-effect transistors (TFETs), static random access memories (SRAMs), dynamic RAM (DRAMs), flash memory, ferroelectric memories, resistitive memories and phase-change memories. We address the basic device principles, the advantages and limitations of these 2D electronic devices, and our perspectives on future developments. TOPICAL REVIEW 2019

Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors.

Abstract: This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.

An Adaptive Thermal Equivalent Circuit Model for Estimating the Junction Temperature of IGBTs

Abstract: Implementation of real-time health assessment and thermal management of insulated gate bipolar transistors (IGBTs) require thermal equivalent circuit models that can be used to predict the junction temperature of the modules. Solder aging in IGBTs has a substantial impact on the accuracy of junction temperatures estimated by the models. This paper proposes an adaptive thermal equivalent circuit model that can estimate the junction temperature of IGBTs with precision under solder aging conditions. First, the solder aging process is monitored in real time by the temperature gradient of the baseplate of the IGBT module, which is easily implemented by placing two thermal sensors at the interface between the baseplate and the cold plate. Then, when the solder aging is detected, the actual junction temperature obtained by an ON-state collector–emitter voltage of the IGBT is utilized to update model parameters based on the thermal behavior of the device. By combining the two stages, the effect of solder aging on the accuracy of the junction temperature estimate is removed in time. Simulation and experimental results are provided to verify the effectiveness of the proposed method.

Investigation on single pulse avalanche failure of SiC MOSFET and Si IGBT

Abstract: In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.

The Temperature Dependence of the Flatband Voltage in High-Power IGBTs

Abstract: This letter experimentally demonstrates the temperature dependence of the flatband voltage ( V FB) in high-power insulated-gate bipolar transistors (IGBTs). The gate voltage during the turn- on delay is shown to fluctuate up to 5 mV/°C as a result of this temperature dependence. We investigate the practical use of this temperature dependence as an addition to the genre of IGBT junction temperature measurement methods known as temperature sensitive electrical parameters (TSEPs). This letter will outline some possible measurement circuits and highlight issues with V FB that may make its use as a TSEP problematic.

Improvement in electrical characteristics of Silicon on Insulator (SOI) transistor using Graphene material

Abstract: This paper presents the electrical characteristics of a short channel Silicon on Insulator (SOI) transistor with a graphene layer. The graphene sheet is used at the bottom of the channel close to the source side and a proportionally heavily p-type retrograde doping implanted in nearly middle of the channel. To increase the gate electrostatic control over the channel we incorporated a high-K material i.e. HfO2 as the gate oxide insulator. Due to Graphene growth and Retrograde Doping in the Channel, we called this structure “GRDC-SOI” transistor. Because graphene sheet has low band gap and high mobility, we used it to increase the on-state current. Engineered p-type retrograde doping utilized for both decreasing off-state current and increasing on-state current. These dopants cause impurity scattering in the depth of the channel and deflect electron movements and decrease off-current. On the other hand, these dopants which are located almost in the middle of the channel can play the role of base in an NPN Bipolar Junction Transistor (BJT), and turn it on and exceed the on-state current. An immense comparison among our proposed device and a device similar to GRDC-SOI but without Graphene sheet (RDC-SOI) and a conventional structure shows that our proposed device has superior electrical characteristics in terms of ION/IOFF ratio, transconductance, subthreshold slope, leakage current, breakdown voltage and short channel effects like hot carriers injection and DIBL. Our analyses demonstrate that GRDC-SOI transistor can open a window for utilizing Graphene material in digital circuits and system on chip applications.

2D Material-Based Vertical Double Heterojunction Bipolar Transistors with High Current Amplification

Abstract: DOI: 10.1002/aelm.201800745 been applied to various types of semiconductor devices, such as lasers, solar cells, high electron mobility transistors, and heterojunction bipolar transistors (HBTs).[3–6] Notably, with a bipolar junction transistor, which is a three-terminal transistor fabricated by connecting two P–N homojunction diodes, there is a trade-off between the current gain and high-frequency ability because of these problems.[3,7] In sharp contrast, HBTs realized using the heterostructure can avoid these trade-offs and improve device performance.[8] HBTs, due to their high power efficiency, uniformity of threshold voltage, and low 1/f noise characteristics, have been widely used in high power amplifiers and high frequency switching devices.[3] It is challenging to realize high-quality hetero-interfaces in heterojunction devices, including HBTs owing to the various growth limitations involving mitigation of diffusion of both dopants and lattice elements. If present, these constraints contribute to performance degradation or even the complete loss of the benefits of incorporating the heterojunction.[3] For instance, III–V compound semiconductors such as GaAs/AlGaAs and GaN/AlGaN used in conventional heterojunction-based devices require high vacuum and high-cost growth equipment such as metalorganic vapor deposition (MOCVD) and molecular beam epitaxy (MBE). This growth is difficult to achieve when the difference of the lattice constants is too significant. Additionally, obstacles such as dislocation defects, strain caused by lattice mismatch, cross-contamination, and inter-diffusion are difficult to overcome. These problems cause device performance deterioration in the form of increased leakage current, a decrease of breakdown voltage, and an increase of recombination rate in HBT devices.[1–3] 2D materials (2DMs) have been studied in various fields over the past decade because of their excellent electrical, thermal, and mechanical properties.[9–13] In particular, heterostructures based on 2DMs have attracted interest because of their weak interlayer bonding, quantum effect, and tunneling, which are differentiated from conventional 3D bulk materials.[10,14] Weak van der Waals interactions of 2DMs can not only easily separate each layer, but can also layer materials regardless of lattice mismatch.[11] Additionally, because 2DMs have a sharp interface and no dangling bonds, heterostructures using 2DMs can solve problems such as atomic diffusion and dislocation propagation, which have been regarded as limitations of existing 3D bulk materials.[11,12] Selection of 2DMs provides The heterojunction bipolar transistor (HBT) differs from the classical homojunction bipolar junction transistor in that each emitter-base-collector layer is composed of a different semiconductor material. 2D material (2DM)based heterojunctions have attracted attention because of their wide range of fundamental physical and electrical properties. Moreover, strain-free heterostructures formed by van der Waals interaction allows true bandgap engineering regardless of the lattice constant mismatch. These characteristics make it possible to fabricate high-performance heterojunction devices such as HBTs, which have been difficult to implement in conventional epitaxy. Herein, NPN double HBTs (DHBTs) are constructed from vertically stacked 2DMs (n-MoS2/p-WSe2/n-MoS2) using dry transfer technique. The formation of the two P–N junctions, base-emitter, and base-collector junctions, in DHBTs, was experimentally observed. These NPN DHBTs composed of 2DMs showed excellent electrical characteristics with highly amplified current modulation. These results are expected to extend the application field of heterojunction electronic devices based on various 2DMs.

Thermal Network Parameter Estimation Using Cooling Curve of IGBT Module

Abstract: This paper proposes a thermal network parameter estimation method for insulated-gate bipolar transistor (IGBT) modules using the junction temperature cooling curve. The proposed method finds the RC parameters of a fourth-order Cauer network by establishing a relationship between RC parameters and time constants of junction temperature response curves. Experimental tests are performed to validate the accuracy of the developed method. Results show that the difference of total thermal resistance between the proposed method and IEC standard is below 2%. Advantages of the proposed method over the existing methods are that the proposed method does not need 1) to know the power loss information of IGBT and 2) to heat the IGBT module up to thermal steady state. In addition, we show that the identified RC parameters can be used for condition monitoring and junction temperature estimation.

A Comparative Study on the Switching Performance of GaN and Si Power Devices for Bipolar Complementary Modulated Converter Legs

Abstract: The commercial mature gallium nitride high electron mobility transistors (GaN HEMT) technology has drawn much attention for its great potential in industrial power electronic applications. GaN HEMT is known for low on-state resistance, high withstand voltage, and high switching frequency. This paper presents comparative experimental evaluations of GaN HEMT and conventional Si insulated gate bipolar transistors (Si IGBTs) of similar power rating. The comparative study is carried out on both the element and converter level. Firstly, on the discrete element level, the steady and dynamic characteristics of GaN HEMT are compared with Si-IGBT, including forward and reverse conducting character, and switching time. Then, the elemental switching losses are analyzed based on measured data. Finally, on a complementary buck converter level, the overall efficiency and EMI-related common-mode currents are compared. For the tested conditions, it is found that the GaN HEMT switching loss is much less than for the same power class IGBT. However, it is worth noting that special attention should be paid to reverse conduction losses in the PWM dead time (or dead band) of complementary-modulated converter legs. When migrating from IGBT to GaN, choosing a dead-time and negative gate drive voltage in conventional IGBT manner can make GaN reverse conducting losses high. It is suggested to use 0 V turn-off gate voltage and minimize the GaN dead time in order to make full use of the GaN advantages.

Van der Waals 2D layered-material bipolar transistor

Abstract: Ultrathin and light heterojunction bipolar transistors based on two-dimensional (2D) layered materials with flexible semiconducting properties have been considered for several electronic applications. In this paper, a van der Waals p-BP/n-MoS2/p-BP BJT is demonstrated. It is fabricated using mechanical exfoliation, where a dry transfer technique is used to stack a vertical double heterojunction. The device structure includes nanoflakes of black phosphorus (BP) and MoS2. The current–voltage characteristics of the common–emitter and common–base configurations are examined. These p-BP/n-MoS2/p-BP bipolar transistors exhibit current–voltage characteristics similar to those of conventional p-n-p bipolar transistors. Devices with thin MoS2 layers show good saturation current–voltage characteristics, and a maximum common–emitter current gain (β = I C /I B ) of approximately 10.1 is obtained at room temperature (300 K). Furthermore, the thickness dependence of the base region (n-MoS2) is investigated for the common–emitter output electrical characteristics (V CE − I C ) of a double heterojunction bipolar transistor in which the emitter is grounded. The collector current decreases as the thickness of n-MoS2 is increased. This study can pave the way for the application of 2D materials as controllable amplifiers in flexible electronics.

Device processing and junction formation needs for ultra-high power Ga2O3 electronics

Abstract: A review is given of the future device processing needs for Ga203 power electronics. The two main devices employed in power converters and wireless charging systems will be vertical rectifiers and metal oxide semiconductor field effect transistors (MOSFETs). The rectifiers involve thick epitaxial layers on conducting substrates and require stable Schottky contacts, edge termination methods to reduce electric field crowding, dry etch patterning in the case of trench structures, and low resistance Ohmic contacts in which ion implantation or low bandgap inter-facial oxides are used to minimize the specific contact resistance. The MOSFETs also require spatially localized doping enhancement for low source/drain contact resistance, stable gate insulators with acceptable band offsets relative to the Ga203 to ensure adequate carrier confinement, and enhancement mode capability. Attempts are being made to mitigate the absence of p-type doping capability for Ga203 by developing p-type oxide heterojunctions with n-type Ga203. Success in this area would lead to minority carrier devices with better on-state performance and a much-improved range of functionality, such as p-i-n diodes, Insulated Gate Bipolar Transistors, and thyristors.

Online Estimation of the Junction Temperature Based on the Gate Pre-Threshold Voltage in High-Power IGBT Modules

Abstract: A model for the online estimation of junction temperature based on the gate pre-threshold voltage in high-power insulated-gate bipolar transistors (IGBTs) was proposed. First, the turn-on behavior and temperature dependence of the gate-emitter voltage during the turn-on delay period were studied. It was revealed that the turn-on waveform of the gate-emitter voltage exhibits a point of inflection after which the voltage between the gate and emitter increases significantly; at this point, the relationship between the voltage and the temperature changes from a positive correlation to a negative correlation. Meanwhile, analyses on the basis of semiconductor physics revealed that the negative correlation between gate-emitter voltage and temperature is caused by the temperature dependence of the flatband voltage. Finally, a model for estimating the junction temperature was established based on a combination of the turn-on delay time and the gate prethreshold voltage which is negatively correlated with the temperature, to eliminate the effect of the bus voltage.

Simulation Study of a Low ON-State Voltage Superjunction IGBT With Self-Biased PMOS

Abstract: In this brief, a novel superjunction (SJ)-insulated-gate bipolar transistor (SJ-IGBT) is proposed and investigated by simulation, where a floating N-base region on the P-pillar region is introduced to form a self-biased PMOS. In the on-state, the PMOS can increase the hole quasi-Fermi potential of the P-pillar region, enhancing the carrier-storage effect in the N-pillar and P-pillar regions and reducing the on-state voltage consequently. In the turn-off transient, because the PMOS can be automatically turned on as a consequence of the potential rise of the P-pillar region with hole accumulation, the proposed SJ-IGBT can be rapidly turned off. The results from TCAD simulation reveal that the on-state voltage of the proposed SJ-IGBT is 46.7% lower than that of the conventional SJ-IGBT with P-pillar shorted with cathode (SJ-IGBT-A) and nearly equivalent to that of the conventional SJ-IGBT with gate on the P-pillar (SJ-IGBT-B). In addition, the off-state breakdown voltage of the proposed SJ-IGBT can roughly keep an identical value with that of SJ-IGBT-A and is 25% higher than that of SJ-IGBT-B. In addition, with the same VON of 1.16 V, the turn-off energy loss of the proposed device is 1.2 mJ/cm2, which is 94.7% lower than that of SJ-IGBT-A and 20% lower than that of SJ-IGBT-B.

A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From −45°C to 125°C

Abstract: We present a 1-V precision voltage reference with a programmable temperature coefficient (“ temp-co ”). The voltage reference is based on a parasitic bipolar junction transistor (BJT) realized within the process steps available in the chosen 7-nm FinFET technology. Details of its characterization and SPICE modeling are presented to provide insight into key device–circuit optimization choices. The trimming techniques needed to cope with process spread together with two curvature compensation techniques are presented. The reference achieves a maximum inaccuracy of ±0.2% and a minimum temp-co of 6 ppm/°C from −45°C to 125°C. Furthermore, its temp-co is digitally programmable between −7 mV/100°C and +8 mV/100°C. Its line regulation is 0.1%/V, and it occupies 0.078 mm2.

A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient

Abstract: This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub...

Miniature High-Power Nanosecond Laser Diode Transmitters Using the Simplest Possible Avalanche Drivers

Abstract: The state-of-the-art long-distance near-infrared optical radars use laser-diode-based miniature pulsed transmitters producing optical pulses of 3–10 ns in duration and peak power typically below 40 W. The duration of the transmitted optical pulses becomes a bottleneck in the task of improving the radar ranging precision, particularly due to the progress made in developing single photon avalanche detectors. The speed of miniature high-current drivers is limited by the speed of the semiconductor switch, either a gallium nitride field-effect transistor, the most popular alternative nowadays, or a silicon avalanche bipolar junction transistor (ABJT), which was traditional in the past. Recent progress in the physical understanding of peculiar 3-D transients promises further enhancement in speed and efficiency of properly modified ABJTs, but that is not the only factor limiting the transmitter speed. We show here that a low-inductance miniature transmitter assembly containing only a specially developed capacitor, a more advanced transistor chip than that used in commercial ABJTs and a laser diode, has allowed peak power from 40 to 180 W to be reached in optical pulses of 1–2 ns in duration without after-pulsing relaxation oscillations. This finding is of interest for compact low-cost, long-distance decimeter-precision lidars, particularly for automotive applications.

Electronic Circuit with Controllable Negative Differential Resistance and its Applications

Abstract: Electronic devices and circuits with negative differential resistance (NDR) are widely used in oscillators, memory devices, frequency multipliers, mixers, etc. Such devices and circuits usually have an N-, S-, or Λ-type current-voltage characteristics. In the known NDR devices and circuits, it is practically impossible to increase the negative resistance without changing the type or the dimensions of transistors. Moreover, some of them have three terminals assuming two power supplies. In this paper, a new NDR circuit that comprises a combination of a field effect transistor (FET) and a simple bipolar junction transistor (BJT) current mirror (CM) with multiple outputs is proposed. A distinctive feature of the proposed circuit is the ability to change the magnitude of the NDR by increasing the number of outputs in the CM. Mathematical expressions are derived to calculate the threshold currents and voltages of the N-type current-voltage characteristics for various types of FET. The calculated current and voltage thresholds are compared with the simulation results. The possible applications of the proposed NDR circuit for designing single-frequency oscillators and voltage-controlled oscillators (VCO) are considered. The designed NDR VCO has a very low level of phase noise and has one of the best values of a standard figure of merit (FOM) among recently published VCOs. The effectiveness of the proposed oscillators is confirmed by the simulation results and the implemented prototype.

SiGe Photo-Transistor for Low-Cost SSMF-Based Radio-Over-Fiber Applications at 850nm

Abstract: This paper investigates the possibility of implementing SiGe Hetero-junction bipolar Photo-Transistor (HPT) within low cost and low power consumption Radio-over-Fiber (RoF) systems based on standard single mode fiber (SSMF) operating in the first optical window for wireless communication networks scenarios. The SiGe HPT under study has potential lower cost compared to standard PIN photo-detectors as it is fabricated through the consolidated SiGe bipolar transistor process technologies, allowing the possible integration with Si-based circuits. Various operation modes of the photo-transistor (such as three-terminals and two-terminals) are investigated, analyzing their impact on the SSMF-based RoF link in terms of gain and noise (including modal noise fluctuations) for a frequency range up to 2.5 GHz. A 20 MHz LTE transmission is finally demonstrated as example of possible applications of the studied RoF link.

500-V Silicon-On-Insulator Lateral IGBT With W-Shaped n-Typed Buffer and Composite p-Typed Collectors

Abstract: A novel 500-V rated silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT), featuring a W-shaped n-typed buffer and p-typed composite collectors, is proposed for the first time in this paper. The composite collectors which consist of a high-doped p+ layer and a low-doped p− layer can maintain a high level of collector-side hole injection in ON-state; the low-doped p− layer combining with the W-shaped buffer provides a low barrier path for electron extraction during turn-off; thus, high current capability and high turn-off speed can be realized at the same time. The measurement results show that 67.3% decrease in turn-off time can be obtained at the expense of only 6.3% of current capability. Compared with the standard SOI-LIGBT, no additional processing steps or process modifications are required for the proposed SOI-LIGBT. The low-doped p− collector is formed simultaneously with the emitter-side p-well while the W-shaped buffer is formed by diffusion overlapping of two neighboring windows. At 125 °C, the proposed SOI-LIGBT exhibits an ON-state voltage drop of 2.48 V, a saturated current density of 420 A/cm2, a turn-off time of $>4~\mu \text{s}$ , allowing significant improvements in power loss, operating frequency, and ruggedness for single-chip intelligent power ICs.

Current Gain Degradation Model of Displacement Damage for Drift BJTs

Abstract: Drift bipolar junction transistors (BJTs), characterized by a graded doping profile in the base region, are susceptible to the recombination in both the base and emitter–base depletion regions when they are damaged by atomic displacement, leading to the gain degradation. The previous model of the gain degradation of BJTs (i.e., Messenger–Spratt model) adopts the assumptions of the neutral base and ideal depletion, which are not valid for the drift BJTs. A drift BJT has an extra build-in electric field which breaks the neutral base condition, and the excess recombination rate is reduced and depends on the drift parameters. Furthermore, the nonideal depletion effects can suppress the excess recombination in the junction region, which will also reduce the susceptibility of the displacement damage (DD). This paper presents a physics-based improvement of the previous model and provides a much better fit to the experimental data of the 3CK3B drift BJTs subjected to deuterium–tritium 14-MeV neutron irradiation. The new model also suggests that the ideal factor of excess base current induced by DD approaches to 1.33 for the BJT technologies with narrow base or operated under low bias conditions.

Junction Temperature Measurement Method for SiC Bipolar Junction Transistor Using Base–Collector Voltage Drop at Low Current

Abstract: This paper proposes an electrical method for estimation of the vertical junction temperature of silicon carbide bipolar junction transistors (SiC BJTs). This measurement method is based on measurement of the base–collector voltage ( V BC) drop at a low current ( V BC(low)) during the turn- off process. This voltage shows both good sensitivity and linearity with respect to temperature. The traditional temperature-sensitive electrical parameter V BE(low) (i.e., the base-emitter voltage at a low current) and an infrared camera are used to compare the characteristics of V BC(low). The results show that use of V BC(low) provides more accurate junction temperature and thermal resistance measurement results, which can then be used to extract the vertical junction temperature of the SiC BJT under test.

High frequency Colpitts’ oscillator: A simple configuration for chaos generation

Abstract: This paper introduces a novel four-component-based high frequency chaotic circuit. The proposed circuit is an implicit common-emitter Colpitts oscillator; hitherto the simplest in the realm of bipolar junction transistor based LC (inductor-capacitor) autonomous chaotic circuits. It consists of a single voltage source in series with a resistor, one bipolar junction transistor, an inductor and a single grounded capacitor. Design procedure takes advantage of an intrinsic capacitance of the transistor to complete the resonant tank. The circuit is mathematically modelled with a three-dimensional autonomous system; theoretical analysis of circuit’s model is presented along with numerical and experimental outcomes. Bifurcation diagrams, Lyapunov exponents, phase portraits and time series revealed that the proposed oscillator is capable of generating striking behaviors such as quasi-sinusoidal orbits, limit cycles and chaos. Overall, a good accordance is found between practice and theory. Comparison between the original Colpitts oscillator and the novel one is done to highlight benefits of the latter. The fact that circuit’s parsimony does not impair chaotic features is of particular interest. Beside well known applications of Colpitts oscillators, this parsimonious version is a good candidate for experimental investigations on networked oscillators and academic purposes owing to its simplicity, low-cost and ease offered in implementation.

A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode

Abstract: This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/°C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 °C to 400 °C. It is proposed that the on/off ratio can be increased by ~1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

IGBT Junction Temperature Measurements: Inclusive of Dynamic Thermal Parameters

Abstract: Insulated gate bipolar transistors (IGBTs) are widely used in new energy fields, such as wind power converters and electric vehicles. The junction temperature characteristics and junction temperature measurements greatly influence the reliability of the IGBT. During switching, the electrical parameters of the IGBT undergo considerable change. The thermo sensitive electrical parameter (TSEP) method has been commonly used to extract junction temperature. The TSEP method has the inherent advantages of being able to take measurements quickly and accurately, in a non-intrusive manner. The junction temperature estimate under the on-state condition cannot reflect the reliability of the IGBT during the dynamic switching process. The solution to this dilemma is to measure the junction temperature using the dynamic TSEP method during the IGBT turn-off process. The junction temperature is measured by the reverse voltage peak between the auxiliary emitter and power emitter, which forms during the IGBT turn-off process. The feasibility of the proposed method has been experimentally verified.

Simplified Estimation of Junction Temperature Fluctuation at the Fundamental Frequency for IGBT Modules Considering Mission Profile

Abstract: The junction temperature at the fundamental frequency cannot be ignored in a lifetime evaluation of insulated-gate bipolar transistors (IGBTs) with a long-term mission profile. Therefore, it is very important in terms of calculation speed and accuracy to simplify the loss curve when calculating the thermal fluctuation at the fundamental frequency. This paper proposes a mathematical analysis method for the junction temperature fluctuation at the fundamental frequency based on an equivalent sinusoidal half-wave loss. The dynamic and static parameters of the devices are tested by an experimental platform, and accurate device loss models are established through a case study of a 1.5 MW direct-drive wind turbine grid-connected model. The accuracy of the proposed calculation model is compared with that of a time-domain simulation and the two-step loss pulse method. Considering different output frequencies, the accuracy of the proposed method is further discussed. Based on actual wind speed data, the proposed method is used to calculate the junction temperature of an IGBT module in a grid-side converter. The results show that the proposed method can improve the accuracy of the reliability evaluation of wind power converters.

Analysis of the Fast-Switching LIGBT With Double Gates and Integrated Schottky Barrier Diode

Abstract: A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity.