Showing papers on "Capacitor published in 2007"

Control and Performance of a Transformerless Cascade PWM STATCOM With Star Configuration

Abstract: This paper presents a three-phase transformerless cascade pulsewidth-modulation (PWM) static synchronous compensator (STATCOM) intended for installation on industrial and utility power distribution systems. It proposes a control algorithm that devotes itself not only to meeting the demand of reactive power but also to voltage balancing of multiple galvanically isolated and floating dc capacitors. The control algorithm based on a phase-shifted carrier modulation strategy is prominent in having no restriction on the cascade number. Experimental waveforms verify that a 200-V 10-kVA cascade PWM STATCOM with star configuration has the capability of inductive to capacitive (or capacitive to inductive) operation at the rated reactive power of 10 kVA within 20 ms while keeping the nine dc mean voltages controlled and balanced even during the transient state.

Full On-Chip CMOS Low-Dropout Voltage Regulator

Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

High Dielectric Performance of Polymer Composite Films Induced by a Percolating Interparticle Barrier Layer

Abstract: The mechanical flexibility and tunable properties of polymer-based materials make them attractive ones for a lot of applications. Exploring polymer-based dielectrics, such as ones used for capacitors and charge-storage applications, with high dielectric constant (high-j) has recently aroused considerable interest. Especially, motivated by higher function and further miniaturization of electronics, embedding (or integrating) polymer-based capacitors into the inner layers of organic printed circuit boards (PCBs) allows packaging substrate miniaturization and better electrical performance, which is a key for organic-based system-on-package technologies. But as capacitors, the relative dielectric constant j of general polymers (being good insulators) is too low (e.g., j< 5).Thus, a key issue is to substantially raise the dielectric constant of the polymers while retaining low dielectric loss. A few strategies have been developed to raise the j of polymer-based materials. A common approach is to add high-j ceramic fillers (e.g., BaTiO3) into a polymer. High loading of the ceramic fillers in the polymer composite, usually over 50 vol %, can increase j by about ten times relative to the polymer matrix, but dramatically decreases the adhesion of the composite (and increases its porosity) thus deteriorating the adaptability between the composite and the organic circuit boards. Another strategy is to fabricate percolative composite capacitors by using conductive fillers (e.g., metal particles). As the volume fraction f of the fillers increases to the vicinity of the percolation threshold fc, j of the composites can be dramatically enhanced as described by the well-known power law

High-Power Density Design of a Soft-Switching High-Power Bidirectional dc–dc Converter

Abstract: A bidirectional dc-dc converter typically consists of a buck and a boost converters. In order to have high-power density, the converter can be designed to operate in discontinuous conducting mode (DCM) such that the passive inductor can be minimized. The DCM operation associated current ripple can be alleviated by interleaving multiphase currents. However, DCM operation tends to increase turnoff loss because of a high peak current and its associated parasitic ringing due to the oscillation between the inductor and the device output capacitance. Thus, the efficiency is suffered with the conventional DCM operation. Although to reduce the turnoff loss a lossless capacitor snubber can be added across the switch, the energy stored in the capacitor needs to be discharged before device is turned on. This paper adopts a gate signal complimentary control scheme to turn on the nonactive switch and to divert the current into the antiparalleled diode of the active switch so that the main switch can be turned on under zero-voltage condition. This diverted current also eliminates the parasitic ringing in inductor current. For capacitor value selection, there is a tradeoff between turnon and turnoff losses. This paper suggests the optimization of capacitance selection through a series of hardware experiments to ensure the overall power loss minimization under complimentary DCM operating condition. According to the suggested design optimization, a 100-kW hardware prototype is constructed and tested. The experimental results are provided to verify the proposed design approach.

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

Abstract: This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

Solid-state image sensor

Abstract: A solid-state image sensor of a charge sorting method used in a time-of-flight measurement method, in which noise derived from background light, which is caused by the reflection light from the subject derived from background light is eliminated, reflection light from the subject derived from a predetermined light source, which is previously set in the solid-state image sensor, is effectively extracted as a signal component to achieve high sensitivity and low noise, which is a solid-state image sensor that is equipped with a plurality of charge-storage sections, discriminates photoelectrons generated by incoming light on the incoming timing and sort to the above-described plurality of charge-storage sections, and measures the timing of the incoming light, in which the sensor has: a plurality of capacitors that capable of conducting to the plurality of charge-storage sections; and a control section that controls a conducted state between the above-described plurality of charge-storage sections and the above-described plurality of capacitors, in which by selectively conducting the above-described plurality of charge-storage sections and the above-described plurality of capacitors by the control of the above-described control section, the difference component of charge stored in the above-described plurality of charge-storage sections is extracted.

Particle Swarm Optimization Based Capacitor Placement on Radial Distribution Systems

Abstract: This paper presents a novel approach that determines the optimal location and size of capacitors on radial distribution systems to improve voltage profile and reduce the active power loss. Capacitor placement & sizing are done by loss sensitivity factors and particle swarm optimization respectively. The concept of loss sensitivity factors and can be considered as the new contribution in the area of distribution systems. Loss sensitivity factors offer the important information about the sequence of potential nodes for capacitor placement. These factors are determined using single base case load flow study. particle swarm optimization is well applied and found to be very effective in radial distribution systems. The proposed method is tested on 10,15, 34, 69 and 85 bus distribution systems.

Comparison of 2.3-kV Medium-Voltage Multilevel Converters for Industrial Medium-Voltage Drives

Abstract: This paper compares the expense of power semiconductors and passive components of a (2.3 kV, 2.4 MVA) two-level, three-level neutral-point-clamped, three-level flying-capacitor, four-level flying-capacitor, and five-level series-connected H-bridge voltage source converter on the basis of the state-of-the-art 6.5-, 3.3-, 2.5-, and 1.7-kV insulated gate bipolar transistors for industrial medium-voltage drives. The power semiconductor losses, the loss distribution, the installed switch power, the design of flying capacitors, and the components of an sine filter for retrofit applications are considered.

Fast-Processing Modulation Strategy for the Neutral-Point-Clamped Converter With Total Elimination of Low-Frequency Voltage Oscillations in the Neutral Point

Abstract: This paper presents a novel modulation strategy for a neutral-point-clamped converter. This strategy overcomes one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point under some operating conditions. The proposed modulation strategy can completely remove this oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads. The algorithm is based on a carrier-based pulsewidth modulation. Nevertheless, it can generate the maximum output-voltage amplitudes that are attainable under linear modulation, such as space-vector modulation. Furthermore, this technique can be implemented with a very simple algorithm and, hence, can be processed very quickly. The only drawback of this strategy is that the switching frequencies of the devices are one third higher than those of standard sinusoidal pulsewidth modulation. A control loop for balancing the voltages on the dc-link capacitors is also proposed. This balancing strategy is designed, so that it does not further increase the switching frequencies of the devices when it is applied to the converter. The proposed modulation technique is verified by simulation and experiment.

Modified Phase-Shifted PWM Control for Flying Capacitor Multilevel Converters

Abstract: The issue of voltage imbalance remains a challenge for the flying capacitor multilevel converter. The phase-shifted pulsewidth modulation (PS-PWM) method has a certain degree of self-balancing properties. However, the method alone is not sufficient to maintain balanced capacitor voltages in practical applications. The paper proposes a closed-loop modified PS-PWM control method by incorporating a novel balancing algorithm. The algorithm takes advantage of switching redundancies to adjust the switching times of selected switching states and thus maintaining the capacitor voltages balanced without adversely affecting the system's performance. Key techniques of the proposed control method, including selection of switching states, calculation of adjusting times for the selected states, and determination of new switching instants of the modified PS-PWM are described and analyzed. Simulation and experimental results are presented to confirm the feasibility of the proposed method

Optimal Modulation of Flying Capacitor and Stacked Multicell Converters Using a State Machine Decoder

Abstract: Modulation of flying capacitor and stacked multicell converters is complicated by the fact that these converters have redundant states that achieve the same phase leg voltage output. Hence, a modulator must use some secondary criteria such as cell voltage balancing to fully define the converter switched state. Alternatively, the modulator can be adapted to directly specify the cell states, such as has been proposed for the harmonically optimal phase disposition (PD) strategy. However the techniques reported to date can lead to uneven distribution of switching transitions between cells, and the synthesis of narrow switched phase leg pulses. This paper presents an improved strategy that decouples the tasks of voltage level selection and switching event distribution. Conventional PD and centered space vector pulsewidth modulation (CSVPWM) strategies are used to define the target voltage level for the converter, and a finite state machine is then used to distribute the transitions to the converter cells in a cyclical fashion. Experimental results for a four-level flying capacitor inverter are presented, verifying that the natural balancing properties of this converter has been preserved, the cell switching utilization is equal and the expected harmonic gains of PD and CSVPWM compared to phase shifted carrier PWM have been achieved

Analysis and Control of DC-Capacitor-Voltage-Drift Phenomenon of a Passive Front-End Five-Level Converter

Abstract: The phenomenon of dc-capacitor-voltage drift is the main technical drawback of a passive front-end multilevel diode-clamped converter (DCC). This paper formulates and analyzes the dc-capacitor-voltage-drift phenomenon of a passive front-end five-level DCC, which operates based on a sinusoidal pulsewidth-modulation (SPWM) switching strategy. The analysis shows dependence of the voltage drift on the modulation index and the ac-side power factor of the DCC. The analysis concludes that an SPWM strategy, without the use of auxiliary power circuitry, is not able to prevent the voltage-drift phenomenon of a five-level DCC. This paper also proposes a space-vector-modulation (SVM)-based switching strategy that takes advantage of redundant switching vectors of the SVM method to counteract the voltage-drift phenomenon. The limit to the range of operation of a five-level DCC, which is based on the proposed SVM strategy, is also presented. The salient feature of the proposed strategy is that it enables voltage balancing of the dc capacitors with no requirements for additional controls or auxiliary-power circuitry, within the specified range of operation. The performance of a DCC under various operating conditions, based on time-domain simulation studies in the MATLAB/SIMULINK environment, is evaluated. This paper demonstrates capability of the proposed SVM strategy to control and maintain voltage balance of dc capacitors.

Single-Chip Multiple-Frequency ALN MEMS Filters Based on Contour-Mode Piezoelectric Resonators

Abstract: This paper reports experimental results on a new class of single-chip multiple-frequency (up to 236 MHz) filters that are based on low motional resistance contour-mode aluminum nitride piezoelectric micromechanical resonators. Rectangular plates and rings are made out of an aluminum nitride layer sandwiched between a bottom platinum electrode and a top aluminum electrode. For the first time, these devices have been electrically cascaded to yield high performance, low insertion loss (as low as 4 dB at 93MHz), and large rejection (27 dB at 236 MHz) micromechanical bandpass filters. This novel technology could revolutionize wireless communication systems by allowing cofabrication of multiple frequency filters on the same chip, potentially reducing form factors and manufacturing costs. In addition, these filters require terminations (1 kOmega termination is used at 236 MHz) that can be realized with on-chip inductors and capacitors, enabling their direct interface with standard 50-Omega systems

A Low-Dropout Regulator for SoC With $Q$ -Reduction

Abstract: A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.

Universal power converter

Abstract: Methods and systems for transforming electric power between two or more portals. Any or all portals can be DC, single phase AC, or multi-phase AC. Conversion is accomplished by a plurality of bi-directional conducting and blocking semiconductor switches which alternately connect an inductor and parallel capacitor between said portals, such that energy is transferred into the inductor from one or more input portals and/or phases, then the energy is transferred out of the inductor to one or more output portals and/or phases, with said parallel capacitor facilitating “soft” turn-off, and with any excess inductor energy being returned back to the input. Soft turn-on and reverse recovery is also facilitated. Said bi-directional switches allow for two power transfers per inductor/capacitor cycle, thereby maximizing inductor/capacitor utilization as well as providing for optimum converter operation with high input/output voltage ratios. Control means coordinate the switches to accomplish the desired power transfers.

Frequency Tunable Microstrip Patch Antenna Using RF MEMS Technology

Abstract: A novel reconfigurable microstrip patch antenna is presented that is monolithically integrated with RF microelectromechanical systems (MEMS) capacitors for tuning the resonant frequency. Reconfigurability of the operating frequency of the microstrip patch antenna is achieved by loading it with a coplanar waveguide (CPW) stub on which variable MEMS capacitors are placed periodically. MEMS capacitors are implemented with surface micromachining technology, where a 1-mum thick aluminum structural layer is placed on a glass substrate with a capacitive gap of 1.5 mum. MEMS capacitors are electrostatically actuated with a low tuning voltage in the range of 0-11.9 V. The antenna resonant frequency can continuously be shifted from 16.05 GHz down to 15.75 GHz as the actuation voltage is increased from 0 to 11.9 V. These measurement results are in good agreement with the simulation results obtained with Ansoft HFSS. The radiation pattern is not affected from the bias voltage. This is the first monolithic frequency tunable microstrip patch antenna where a CPW stub loaded with MEMS capacitors is used as a variable load operating at low dc voltages

Algorithms for Controlling Both the DC Boost and AC Output Voltage of Z-Source Inverter

Abstract: This paper aims to achieve good performance for both the dc boost and the ac output voltage control of the Z-source inverter (ZSI). The algorithm to control linearly the capacitor voltage is suggested in order to improve the transient response for dc boost control of the ZSI. The peak value of the ac output voltage is used to control exactly the ac output voltage to its desired level. A modified space vector pulsewidth modulation scheme is applied to control the shoot-through time for boosting dc voltage. The proposed algorithms are verified with simulation and experiment with a 32-bit digital signal processor.

Electrical Energy Density and Discharge Characteristics of a Poly(vinylidene fluoride-chlorotrifluoroethylene)Copolymer

Abstract: The high electric displacement (D>0.1 C/m2) and breakdown field (600 MV/m) in polyvinylidene fluoride based polymers suggest high electrical energy density in this class of polymers. By defect modifications which reduce or eliminate the remnant polarization in the polymer, a high electrical energy density can indeed be obtained. This paper shows that in properly prepared P(VDF-CTFE) copolymer film capacitors, an electrical energy density ~25 J/cm3 can be obtained with a breakdown field higher than 600 MV/m. The dielectric and discharge behavior of the polymer films were investigated. The results reveal that there are strong frequency dispersions in both the dielectric and discharge behavior. The dielectric constant decreases with frequency and the discharged energy density is also reduced at shorted discharge time (~1 mus) due to increased ESR for fast discharge. The results indicate the potential of this class of polymers for high energy density capacitors and suggest the need for further tuning of the polymer compositions to reduce the frequency dispersion.

Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications

Abstract: This paper presents a voltage scalable switched capacitor (SC) DC-DC converter which employs on-chip charge- transfer capacitors. The DC-DC converter makes use of multiple topologies to achieve scalable voltage generation while minimizing conduction loss and a technique called divide-by-3 switching to minimize the loss due to bottom-plate parasitics. It also uses automatic frequency scaling to reduce switching losses. The converter employs an all digital control which consumes no static power. The voltage scalable SC DC-DC converter with integrated on-chip charge-transfer capacitors was implemented in a 0.18 mum CMOS process and achieves above 70% efficiency over a wide range of load powers from 5 muW to 1 mW, while delivering load voltages from 300 mV to 1.1 V. The active area consumed by the converter is 0.57 mm2.

Rectifier circuit, power supply circuit, and semiconductor device

Abstract: It is an object of the present invention to provide a rectifier circuit that can suppress deterioration or dielectric breakdown of a semiconductor element due to excessive current. A rectifier circuit of the present invention includes at least a first capacitor, a second capacitor, and a diode which are sequentially connected in series in a path which connects an input terminal and one of two output terminals, and a transistor. The second capacitor is connected between one of a source region and a drain region and a gate electrode of the transistor. Further, the other one of the source region and the drain region and the other one of two output terminals are connected each other.

Switched capacitor converters

Abstract: A switched capacitor converter has a supply voltage input, an output circuit with one or more load capacitors, a semiconductor switch network. The switch network is connected at a switch junction point and across the voltage input, and has one or more pairs of said first and second switches. Each pair of switches is associated with one of the load capacitors and each pair is connected in series. The converter also has a charging capacitor network connected across the semiconductor switch network and across the voltage input. The charging capacitor network has one or more charging capacitors and inductances connected between the switch junction point and the output circuit. Each of the charging capacitors and inductances is associated with one of the load capacitors. The load capacitors are each charged by the associated charging capacitor when the associated first switch is closed and the associated second switch is open. And the load capacitors are each discharged by the associated inductance when the associated first switch is closed and the associated second switch is open.

Low-voltage operation of ferroelectric poly(vinylidene fluoride-trifluoroethylene) copolymer capacitors and metal-ferroelectric-insulator-semiconductor diodes

Abstract: Exceptionally low-voltage operation of organic ferroelectric capacitors and diodes was demonstrated. Ferroelectric polyvinylidene fluoride-trifluoroethylene [P(VDF-TrFE)] thin films were prepared by the solvent-cast method. Metal-ferroelectric-metal capacitors with 60-nm-thick P(VDF-TrFE) films exhibited well-saturated hysteresis curves whose coercive voltage (Vc) and remanent polarization (Pr) were 2.0V and 11.9μC∕cm2, respectively. The authors also fabricated metal-ferroelectric-insulator-semiconductor diodes with 100-nm-thick P(VDF-TrFE) films. Rectangular-shaped capacitance-voltage (C-V) hysteresis loops were obtained with a voltage sweep range narrower than 5V. The maximum memory window of 4.7V was achieved.

A Wireless, Passive Sensor for Quantifying Packaged Food Quality.

Abstract: Norinse Technologies LLC, Hancock, MI 49930, USA. * Author to whom correspondence should be addressed. E-mail: kgong@mtu.edu Received: 23 August 2007 / Accepted: 28 August 2007 / Published: 5 September 2007 Abstract: This paper describes the fabrication of a wireless, passive sensor based on an inductive-capacitive resonant circuit, and its application for in situ monitoring of the quality of dry, packaged food such as cereals, and fried and baked snacks. The sensor is made of a planar inductor and capacitor printed on a paper substrate. To monitor food quality, the sensor is embedded inside the food package by adhering it to the package’s inner wall; its response is remotely detected through a coil connected to a sensor reader. As food quality degrades due to increasing humidity inside the package, the paper substrate absorbs water vapor, changing the capacitor’s capacitance and the sensor’s resonant frequency. Therefore, the taste quality of the packaged food can be indirectly determined by measuring the change in the sensor’s resonant frequency. The novelty of this sensor technology is its wireless and passive nature, which allows in situ determination of food quality. In addition, the simple fabrication process and inexpensive sensor material ensure a low sensor cost, thus making this technology economically viable. Keywords: Resonant circuit sensor, food quality monitoring, wireless, passive. 1. Introduction Dry, packaged food usually requires an airtight package to maintain its quality and ensure food safety. For example, hermitically sealed bags are essential for dry snacks such as potato chips, corn

Capacitor-loaded split ring resonators as tunable metamaterial components

Abstract: Transmission through split ring resonator (SRR) structures loaded with capacitors is investigated both experimentally and numerically. Magnetic resonance frequency (ωm) is observed to shift to lower frequencies when capacitors are mounted to the various capacitive regions of the SRR structure. The amount of change in ωm depends strongly on the place where the capacitors are loaded. The magnetic resonance is obtained at 0.99GHz with subwavelength SRR size of λ∕42 when the capacitor (C=2.2pF) is integrated at the split region of the outer ring.

A Low-Power Blocking-Capacitor-Free Charge-Balanced Electrode-Stimulator Chip With Less Than 6 nA DC Error for 1-mA Full-Scale Stimulation

Abstract: Large dc blocking capacitors are a bottleneck in reducing the size and cost of neural implants. We describe an electrode-stimulator chip that removes the need for large dc blocking capacitors in neural implants by achieving precise charge-balanced stimulation with <6 nA of dc error. For cochlear implant patients, this is well below the industry's safety limit of 25 nA. Charge balance is achieved by dynamic current balancing to reduce the mismatch between the positive and negative phases of current to 0.4%, followed by a shorting phase of at least 1 ms between current pulses to further reduce the charge error. On +6 and -9 V rails in a 0.7-mum AMI high voltage process, the power consumption of a single channel of this chip is 47 muW when biasing power is shared by 16 channels.

An Interleaved Winding-Coupled Boost Converter With Passive Lossless Clamp Circuits

Abstract: An interleaved winding-coupled boost converter is proposed in order to realize ZCS turn-on condition and to achieve high step-up gain. The voltage gain is extended easily and the voltage stress on the switches is reduced with different turns ratios of the coupled inductors. The output diode reverse-recovery problem is alleviated due to the inherent leakage inductor of the winding-coupled inductors. The simple but effective passive lossless clamp circuits are introduced to limit the voltage stress on the switches when they turn off so that the low-voltage, high-performance devices with low conduction resistor can be used in the proposed converter to reduce the relative losses. The leakage energy is ultimately recovered to the load. The high efficiency of 90.7% at full load and the maximum efficiency of 92.6% are achieved in a 1-kW 40-V-input-to-380-V-output prototype for front-end application. There is more than 10% efficiency improvement with the passive lossless clamp circuits compared to the case with RCD dissipated snubbers. The efficiency of 5% improvement at full load is achieved with the proposed converter with passive lossless circuits compared to the conventional interleaved boost converter.