Showing papers on "Field-effect transistor published in 2000"

A soluble and air-stable organic semiconductor with high electron mobility

Abstract: Electronic devices based on organic semiconductors offer an attractive alternative to conventional inorganic devices due to potentially lower costs, simpler packaging and compatibility with flexible substrates. As is the case for silicon-based microelectronics, the use of complementary logic elements-requiring n- and p-type semiconductors whose majority charge carriers are electrons and holes, respectively-is expected to be crucial to achieving low-power, high-speed performance. Similarly, the electron-segregating domains of photovoltaic assemblies require both n- and p-type semiconductors. Stable organic p-type semiconductors are known, but practically useful n-type semiconductor materials have proved difficult to develop, reflecting the unfavourable electrochemical properties of known, electron-demanding polymers. Although high electron mobilities have been obtained for organic materials, these values are usually obtained for single crystals at low temperatures, whereas practically useful field-effect transistors (FETs) will have to be made of polycrystalline films that remain functional at room temperature. A few organic n-type semiconductors that can be used in FETs are known, but these suffer from low electron mobility, poor stability in air and/or demanding processing conditions. Here we report a crystallographically engineered naphthalenetetracarboxylic diimide derivative that allows us to fabricate solution-cast n-channel FETs with promising performance at ambient conditions. By integrating our n-channel FETs with solution-deposited p-channel FETs, we are able to produce a complementary inverter circuit whose active layers are deposited entirely from the liquid phase. We expect that other complementary circuit designs can be realized by this approach as well.

Fabrication and performance of GaN electronic devices

Abstract: GaN and related materials (especially AlGaN) have recently attracted a lot of interest for applications in high power electronics capable of operation at elevated temperatures. Although the growth and processing technology for SiC, the other viable wide bandgap semiconductor material, is more mature, the AlGaInN system offers numerous advantages. These include wider bandgaps, good transport properties, the availability of heterostructures (particularly AlGaN/GaN), the experience base gained by the commercialization of GaN-based laser and light-emitting diodes and the existence of a high growth rate epitaxial method (hydride vapor phase epitaxy) for producing very thick layers or even quasi-substrates. These attributes have led to rapid progress in the realization of a broad range of GaN electronic devices, including heterostructure field effect transistors (HFETs), Schottky and p–i–n rectifiers, heterojunction bipolar transistors (HBTs), bipolar junction transistors (BJTs) and metal-oxide semiconductor field effect transistors (MOSFETs). This review focuses on the development of fabrication processes for these devices and the current state-of-the-art in device performance, for all of these structures. We also detail areas where more work is needed, such as reducing defect densities and purity of epitaxial layers, the need for substrates and improved oxides and insulators, improved p-type doping and contacts and an understanding of the basic growth mechanisms.

AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor

Abstract: We report on the AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (MOS-HFET) and present the results of the comparative studies of this device and a base line AlGaN/GaN heterostructure field effect transistor (HFET). For a 5-/spl mu/ source-to-drain opening, the maximum current was close to 600 mA/mm for both devices. The gate leakage current for the MOS-HFET was more than six orders of magnitude smaller than for the HFET.

The Physical Chemistry of Organic Field-Effect Transistors

Abstract: This review covers fabrication and performance of organic-based field-effect transistors (FETs). The electronic states of organic solids, crystal growth processes, film alignment and morphology, and charge transport mechanisms are discussed. Discontinuities in the active layers and nonidealities in the device behavior are highlighted, and are presented as opportunities for further physical chemistry investigation.

Amplifying quantum signals with the single-electron transistor

Abstract: Transistors have continuously reduced in size and increased in switching speed since their invention in 1947. The exponential pace of transistor evolution has led to a revolution in information acquisition, processing and communication technologies. And reigning over most digital applications is a single device structure--the field-effect transistor (FET). But as device dimensions approach the nanometre scale, quantum effects become increasingly important for device operation, and conceptually new transistor structures may need to be adopted. A notable example of such a structure is the single-electron transistor, or SET. Although it is unlikely that SETs will replace FETs in conventional electronics, they should prove useful in ultra-low-noise analog applications. Moreover, because it is not affected by the same technological limitations as the FET, the SET can approach closely the quantum limit of sensitivity. It might also be a useful read-out device for a solid-state quantum computer.

Ambipolar pentacene field-effect transistors and inverters.

Abstract: Organic field-effect transistors based on pentacene single crystals, prepared with an amorphous aluminum oxide gate insulator, are capable of ambipolar operation and can be used for the preparation of complementary inverter circuits. The field-effect mobilities of carriers in these transistors increase from 2.7 and 1.7 square centimeters per volt per second at room temperature up to 1200 and 320 square centimeters per volt per second at low temperatures for hole and electron transport, respectively, following a power-law dependence. The possible simplification of the fabrication process of complementary logic circuits with these transistors, together with the high carrier mobilities, may be seen as another step toward applications of plastic electronics.

Field effect transistors with SrTiO3 gate dielectric on Si

Abstract: SrTiO3 has been grown epitaxially by molecular beam epitaxy on Si The capacitance of this 110 A dielectric film is electrically equivalent to less than 10 A of SiO2 This structure has been used to make capacitors and metal oxide semiconductor field effect transistors The interface trap density between the SrTiO3 and the Si is 64×1010 states/cm2 eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively The gate leakage in these devices is two orders of magnitude smaller than a similar SiO2 gate dielectric field effect transistor

Active matrix type display apparatus and drive circuit thereof

Abstract: Each of picture elements comprises an input transistor for accepting a signal current from a data line when a scanning line is selected, a conversion transistor for converting the signal current into a voltage and for holding thus converted voltage, and a drive transistor for driving a light emitting device with drive current corresponding to the converted voltage. The conversion transistor flows the signal current to its channel to generate the voltage corresponding to the converted voltage and a capacitor to restrain the generated voltage. Further the drive transistor flows the drive current corresponding to the voltage stored in the capacitor. In this case the threshold voltage of the drive transistor is set not to be smaller than the threshold voltage of the conversion transistor, and thereby a leakage current flowing through the light emitting device is suppressed.

Gate leakage current mechanisms in AlGaN/GaN heterostructure field-effect transistors

Abstract: Gate leakage currents in AlGaN/GaN heterostructure field-effect transistor (HFET) structures with conventional and polarization-enhanced barriers have been studied Comparisons of extensive gate leakage current measurements with two-dimensional simulations show that vertical tunneling is the dominant mechanism for gate leakage current in the standard-barrier HFET and that the enhanced-barrier structure suppresses this mechanism in order to achieve a reduced leakage current An analytical model of vertical tunneling in a reverse-biased HFET gate-drain diode is developed to evaluate the plausibility of this conclusion The model can be fit to the measured data, but suggests that additional leakage mechanisms such as lateral tunneling from the edge of the gate to the drain or defect-assisted tunneling also contribute to the total leakage current The vertical tunneling current mechanism is shown to be more significant to the gate leakage current in III–V nitride HFETs than in HFETs fabricated in other III–V

Semiconductor Devices: Basic Principles

Abstract: Electrons in Solids Electrons in Semiconductors Carrier Dynamics in Semiconductors Processing of Devices: A Review Junctions in Semiconductors: P-N Diodes Semiconductor Junctions with Metals and Insulators Bipolar Junction Transistors Field Effect Transistors: JFET/MESFET Field Effect Transistors: MOSFET MOSFET: Technology Driver Semiconductor Optoelectronics Appendices Index

Minimally-patterned semiconductor devices for display applications

Abstract: A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The semiconductor layer is preferably unpatterned. In various display applications, the geometry of the transistors is selected to provide acceptable leakage currents. In a preferred embodiment, the transistor array is employed in an encapsulated electrophoretic display.

Programmable memory address decode array with vertical transistors

Abstract: A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F2 is needed per bit of logic, where F is the minimum lithographic feature size.

Field-effect transistor made of individual V2O5 nanofibers

Abstract: A field-effect transistor (FET) with a channel length of ∼100 nm was constructed from a small number of individual V2O5 fibers of the cross section 1.5 nm×10 nm. At low temperature, the conductance increases as the gate voltage is changed from negative to positive values, characteristic of a FET with n-type enhancement mode. The carrier mobility, estimated from the low-field regime, is found to increase from 7.7×10−5 cm2/V s at T=131 K to 9.6×10−3 cm2/V s at T=192 K with an activation energy of Ea=0.18 eV. The nonohmic current/voltage dependence at high electric fields was analyzed in the frame of small polaron hopping conduction, yielding a nearest-neighbor hopping distance of ∼4 nm.

Cellular trench-gate field-effect transistors

Abstract: A cellular trench-gate field-effect transistor comprises a field plate (38) on dielectric material (28) in a perimeter trench (18). The dielectric material (28) forms a thicker dielectric layer than the gate dielectric layer (21) in the array trenches (11). The field plate (38) is connected to the source (3) or trench-gate (31) of the transistor and acts inwardly towards the cellular array rather than outwardly towards the body perimeter (15) because of its presence on the inside wall (18a) of the trench (18) without acting on any outside wall (18b). The array and perimeter trenches (11, 18) are sufficiently closely spaced, and the intermediate areas (4a, 4b) of the drain drift region (4) are sufficiently lowly doped, that the depletion layer (40) formed in the drain drift region (4) in the blocking state of the transistor depletes the whole of these intermediate areas between neighbouring trenches at a voltage less than the breakdown voltage. This arrangement reduces the risk of premature breakdown that can occur at high field points in the depletion layer (40), especially at the perimeter of the cellular array.

Detection of single photons using a field-effect transistor gated by a layer of quantum dots

Abstract: We demonstrate that the conductance of a field-effect transistor (FET) gated by a layer of nanometer-sized quantum dots is sensitive to the absorption of single photons. Rather than relying upon an avalanche process, as in conventional semiconductor single-photon detectors, the gain in this device derives from the fact that the conductivity of the FET channel is very sensitive to the photoexcited charge trapped in the dots. This phenomenon may allow a type of three-terminal single-photon detector to be developed based upon FET technology.

Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology

Abstract: For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top surface and the first and second side surfaces of the pillar and at the sidewalls and the bottom wall of the recess, for a gate length along the length of the pillar. In addition, a gate electrode material is deposited on the gate dielectric material to surround the pillar at the top surface and the first and second side surfaces of the pillar and to fill the recess, for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar.

High hole mobility in Si0.17Ge0.83 channel metal–oxide–semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition

Abstract: We report on effective hole mobility in SiGe-based metal–oxide–semiconductor (MOS) field-effect transistors grown by low-energy plasma-enhanced chemical vapor deposition The heterostructure layer stack consists of a strained Si017Ge083 alloy channel on a thick compositionally-graded Si052Ge048 buffer Structural assessment was done by high resolution x-ray diffraction Maximum effective hole mobilities of 760 and 4400 cm2/Vs have been measured at 300 and 77 K, respectively These values exceed the hole mobility in a conventional Si p-MOS device by a factor of 4 and reach the mobility data of conventional Si n-MOS transistors

Coulomb-blockade transport in single-crystal organic thin-film transistors

Abstract: Coulomb-blockade transport—whereby the Coulomb interaction between electrons can prohibit their transport around a circuit—occurs in systems in which both the tunnel resistance, RT, between neighbouring sites is large (≫h/e2) and the charging energy, EC (EC = e2/2C, where C is the capacitance of the site), of an excess electron on a site is large compared to kT. (Here e is the charge of an electron, k is Boltzmann's constant, and h is Planck's constant.) The nature of the individual sites—metallic, superconducting, semiconducting or quantum dot—is to first order irrelevant for this phenomenon to be observed1. Coulomb blockade has also been observed in two-dimensional arrays of normal-metal tunnel junctions2, but the relatively large capacitances of these micrometre-sized metal islands results in a small charging energy, and so the effect can be seen only at extremely low temperatures. Here we demonstrate that organic thin-film transistors based on highly ordered molecular materials can, to first order, also be considered as an array of sites separated by tunnel resistances. And as a result of the sub-nanometre sizes of the sites (the individual molecules), and hence their small capacitances, the charging energy dominates at room temperature. Conductivity measurements as a function of both gate bias and temperature reveal the presence of thermally activated transport, consistent with the conventional model of Coulomb blockade.

Scattering mechanisms limiting two-dimensional electron gas mobility in Al0.25Ga0.75N/GaN modulation-doped field-effect transistors

Abstract: In order to characterize the electron transport properties of the two-dimensional electron gas (2DEG) in AlGaN/GaN modulation-doped field-effect transistors, channel magnetoresistance has been measured in the magnetic field range of 0–12 T, the temperature range of 25–300 K, and gate bias range of +0.5 to −2.0 V. By assuming that the 2DEG provides the dominant contribution to the total conductivity, a one-carrier fitting procedure has been applied to extract the electron mobility and carrier sheet density at each particular value of temperature and gate bias. Consequently, the electron mobility versus 2DEG sheet density has been obtained for each measurement temperature. Theoretical analysis of these results suggests that for 2DEG densities below 7×1012 cm−2, the electron mobility in these devices is limited by interface charge, whereas for densities above this level, electron mobility is dominated by scattering associated with the AlGaN/GaN interface roughness.

A light-emitting field-effect transistor.

Abstract: We report here on the structure and operating characteristics of an ambipolar light-emitting field-effect transistor based on single crystals of the organic semiconductor α-sexithiophene. Electrons and holes are injected from the source and drain electrodes, respectively. Their concentrations are controlled by the applied gate and drain-source voltages. Excitons are generated, leading to radiative recombination. Moreover, above a remarkably low threshold current, coherent light is emitted through amplified spontaneous emission. Hence, this three-terminal device is the basis of a very promising architecture for electrically driven laser action in organic semiconductors.

Thin-film field-effect transistor with organic-inorganic hybrid semiconductor requiring low operating voltages

Abstract: A thin film transistor (TFT) device structure based on an organic-inorganic hybrid semiconductor material, that exhibits a high field effect mobility, high current modulation at lower operating voltages than the current state of the art organic-inorganic hybrid TFT devices. The structure comprises a suitable substrate disposed with the following sequence of features: a set of conducting gate electrodes covered with a high dielectric constant insulator, a layer of the organic-inorganic hybrid semiconductor, sets of electrically conducting source and drain electrodes corresponding to each of the gate lines, and an optional passivation layer that can overcoat and protect the device structure. Use of high dielectric constant gate insulators exploits the gate voltage dependence of the organic-inorganic hybrid semiconductor to achieve high field effect mobility levels at very low operating voltages. Judicious combinations of the choice of this high dielectric constant gate insulator material and the means to integrate it into the organic-inorganic hybrid based TFT structure are taught that would enable easy fabrication on glass or plastic substrates and the use of such devices in flat panel display applications.

MOS field-effect transistor with auxiliary electrode

Abstract: A MOS field-effect transistor is disclosed having a low on resistance Ron, in which auxiliary electrodes composed of polycrystalline silicon surrounded by an insulating layer are provided in the drift path between semiconductor regions of one conduction type. A MOSFET according to the invention may be fabricated in a simple manner compared to conventional MOSFETs using, for example, trench processing technology.

Trap characterization by gate-drain conductance and capacitance dispersion studies of an AlGaN/GaN heterostructure field-effect transistor

Abstract: Gate-drain capacitance and conductance measurements were performed on an Al0.15Ga0.85N/GaN heterostructure field-effect transistor to study the effects of trap states on frequency-dependent device characteristics. By varying the measurement frequency in addition to the bias applied to the gate, the density and time constants of the trap states have been determined as functions of gate bias. Detailed analysis of the frequency-dependent capacitance and conductance data was performed assuming models in which traps are present at the heterojunction (interface traps), in the AlGaN barrier layer (bulk traps), and at the gate contact (metal–semiconductor traps). Bias-dependent measurements were performed at voltages in the vicinity of the transistor threshold voltage, yielding time constants on the order of 1 μs and trap densities of approximately 1012 cm−2 eV−1.

Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Field-effect transistor for alleviating short-channel effects

Abstract: An IGFET ( 40 or 42 ) has a channel zone ( 64 or 84 ) situated in body material ( 50 ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( 60 and 62 or 80 and 82 ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.4 μm deep into the body material.

Molecular wire transistor (MWT)

Abstract: Bipolar and field effect molecular wire transistors are provided. The molecular wire transistor comprises a pair of crossed wires, with at least one of the wires comprising a doped semiconductor material. The pair of crossed wires forms a junction where one wire crosses another, one wire being provided with Lewis acid functional groups and the other wire being provided with Lewis base functional groups. If both wires are doped semiconductor, such as silicon, one is P-doped and the other is N-doped. One wire of a given doping comprises the emitter and collector portions and the other wire comprises the base portion, which is formed by modulation doping on the wire containing the emitter and collector at the junction where the wires cross and between the emitter and collector portions, thereby forming a bipolar transistor. Both NPN and PNP bipolar transistors may be formed. Analogously, one wire may comprise doped semiconductor, such as silicon, and the other wire a metal, the doped silicon wire forming the source and drain and the metal wire forming the gate by modulation doping on the doped silicon wire where the wires cross, between the source and drain, to form a field effect transistor. Both P-channel and N-channel FETs may be formed. The construction of both bipolar transistors and FETs on a nanometer scale, which are self-aligned and modulation-doped, is thereby enabled.

A plasma process for ultrafast deposition of SiGe graded buffer layers

Abstract: Low energy plasma enhanced chemical vapor deposition (LEPECVD) has been applied to the synthesis of Si-modulation doped field effect transistor structures, comprising a SiGe relaxed buffer layer and a modulation doped strained Si channel. A growth rate of at least 5 nm/s for the relaxed SiGe buffer layer is well above that obtainable by any other technique. Due to the low ion energies involved in LEPECVD, ion damage is absent, despite a huge plasma density. The structural quality of the LEPECVD grown SiGe buffer layers is comparable to that of state-of-the-art material. The electronic properties of the material were evaluated by growing modulation doped Si quantum wells on the buffer layers. We obtain a low temperature (2 K) Hall mobility of μH=2.5×104 cm2/Vs for the electrons in the Si channel at an electron sheet density of ns=8.6×1011 cm−2.

Semiconductor device and semiconductor substrate

Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.