Showing papers on "Memistor published in 2015"

VTEAM: A General Model for Voltage-Controlled Memristors

Abstract: Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to their nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this brief, some applications require voltage-controlled memristors to operate properly. In this brief, a Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage-controlled memristors. The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors. The VTEAM model has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled memristors. The VTEAM model is accurate (below 1.5% in terms of the relative root-mean-square error) and computationally efficient as compared with existing memristor models and experimental results describing different memristive technologies.

Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training

Abstract: Learning in multilayer neural networks (MNNs) relies on continuous updating of large matrices of synaptic weights by local rules. Such locality can be exploited for massive parallelism when implementing MNNs in hardware. However, these update rules require a multiply and accumulate operation for each synaptic weight, which is challenging to implement compactly using CMOS. In this paper, a method for performing these update operations simultaneously (incremental outer products) using memristor-based arrays is proposed. The method is based on the fact that, approximately, given a voltage pulse, the conductivity of a memristor will increment proportionally to the pulse duration multiplied by the pulse magnitude if the increment is sufficiently small. The proposed method uses a synaptic circuit composed of a small number of components per synapse: one memristor and two CMOS transistors. This circuit is expected to consume between 2% and 8% of the area and static power of previous CMOS-only hardware alternatives. Such a circuit can compactly implement hardware MNNs trainable by scalable algorithms based on online gradient descent (e.g., backpropagation). The utility and robustness of the proposed memristor-based circuit are demonstrated on standard supervised learning tasks.

Memristor-Based Cellular Nonlinear/Neural Network: Design, Analysis, and Applications

Abstract: Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current–voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

Memristor based computation-in-memory architecture for data-intensive applications

Abstract: One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.

Vortex: variation-aware training for memristor X-bar

Abstract: Recent advances in development of memristor devices and crossbar integration allow us to implement a low-power on-chip neuromorphic computing system (NCS) with small footprint. Training methods have been proposed to program the memristors in a crossbar by following existing training algorithms in neural network models. However, the robustness of these training methods has not been well investigated by taking into account the limits imposed by realistic hardware implementations. In this work, we present a quantitative analysis on the impact of device imperfections and circuit design constraints on the robustness of two popular training methods -- "close-loop on-device" (CLD) and "open-loop off-device" (OLD). A novel variation-aware training scheme, namely, Vortex, is then invented to enhance the training robustness of memristor crossbar-based NCS by actively compensating the impact of device variations and optimizing the mapping scheme from computations to crossbars. On average, Vortex can significantly improve the test rate by 29.6% and 26.4%, compared to the traditional OLD and CLD, respectively.

A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses

Abstract: Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.

A 16 Hz–160 kHz memristor emulator circuit

Abstract: This paper reports experimental tests of a memristor emulator circuit employing a double output second generation current conveyor, a four quadrant analog multiplier, a capacitor and two resistors. First, the behavioral model of the proposed emulator circuit is derived, including parasitic elements and exhibiting that the memristance of a charge-controlled memristor is modeled as a first-order function. Subsequently, an analysis on the frequency performance is done, showing not only that the frequency-dependent pinched hysteresis loop in the current-versus-voltage plane holds up to 160 kHz, but a guideline for choosing the numerical values of the passive elements according to the desired operating frequency is also given. Afterwards, the emulator circuit is built with commercially available devices, confirming good agreement among theoretical simulations, HSPICE results and experimental tests. Furthermore, we show that by using a simple switch, the emulator circuit can be configured as decremental or incremental memristor in order to be used in future applications such as sensors, cellular neural networks, chaotic systems, programmable analog circuits and nonvolatile memory devices.

A continuous-level memristor emulator and its application in a multivibrator circuit

Abstract: This paper presents a new memristor emulator circuit. The circuit is built around the current-feedback operational-amplifier and exploits the nonlinear transfer characteristic of the operational transconductance amplifier to provide continuous change in the memresistance. This is in contrast with many of the available memristor emulators which can provide only binary memresistance levels. Moreover, the emulator enjoys a low impedance input and is suitable for current driving rather than voltage driving. The functionality of the proposed memristor emulator is confirmed by implementing a well-known reactance-less multivibrator circuit. Experimentally obtained results are included.

Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory

Abstract: Memory manufactures are facing the challenges of technology scaling beyond 1xnm node DRAM and NAND flash memory. Even though we are managing to overcome patterning issue, we are still fighting against cost reduction and electrical limitation. In this paper, the scaling limitations and challenges of both DRAM and NAND are reviewed, and the future prospects with promising solutions are also addressed for high density DRAM and 3D NAND flash memory.

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories

Abstract: Memristors are an attractive option for use in future memory architectures but are prone to high defect densities due to the nondeterministic nature of nanoscale fabrication. Several works discuss memristor fault models and testing. However, none of them considers the memristor as a multilevel cell (MLC). The ability of memristors to function as an MLC allows for extremely dense, low-power memories. Using a memristor as an MLC introduces fault mechanisms that cannot occur in typical two-level memory cells. In this paper, we develop fault models for memristor-based MLC crossbars. The typical approach to testing a memory subsystem entails testing one memory cell at a time. However, this testing strategy is time consuming and does not scale for dense, memristor memories. We propose an efficient testing technique that exploits sneak-paths inherent in crossbar memories to test several memory cells simultaneously. In this paper, we integrate solutions for detecting and locating faults in memristors. We develop a power aware built-in self-test solution to detect these faults. We also propose a hybrid diagnosis scheme that uses a combination of sneak-path and March testing to reduce diagnosis time. The proposed schemes enable and leverage sneak-paths during fault detection and diagnosis modes, while disabling sneak-paths during normal operation. The proposed hybrid scheme reduces fault detection and diagnosis time by 24.69% and 28%, respectively, compared to traditional March tests.

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

Abstract: A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.

Overview of emerging memristor families from resistive memristor to spintronic memristor

Abstract: Memristor is a fundamental circuit element in addition to resistor, capacitor, and inductor. As it can remember its resistance state even encountering a power off, memristor has recently received widespread applications from non-volatile memory to neural networks. The current memristor family mainly comprises resistive memristor, polymeric memristor, ferroelectric memristor, manganite memristor, resonant-tunneling diode memristor, and spintronic memristor in terms of the materials the device is made of. In order to help researcher better understand the physical principles of the memristor, and thus to provide a promising prospect for memristor devices, this paper presents an overview of memristor materials properties, switching mechanisms, and potential applications. The performance comparison among different memristor members is also given.

Fault modeling and testing of 1T1R memristor memories

Abstract: Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.

A memristor emulator as a replacement of a real memristor

Abstract: In this paper, we propose a memristor emulator that embraces most of features of a real memristor. The important features that a memristor emulator should include are a sufficiently wide range of memristance, bimodal operability of pulse and continuous signal inputs, a long period of nonvolatility, floating operation, operability with other devices, and the ability to be implemented with off-the-shelf devices. The proposed memristor emulator circuit contains all of these features. Specifically, the small variation range of memristance and the nonfloating operation that limit conventional memristor emulators are improved significantly. It is designed to be built with off-the-shelf electronics devices.

What are Memristor, Memcapacitor, and Meminductor?

Abstract: Memristor, memcapacitor, and meminductor are new fundamental circuit elements, whose properties depend on the history of devices. This paper presents the physical analysis of these memory devices. Three simple examples are given for the memristor, memcapacitor, and meminductor, and are then generalized to reveal their general physical origin. It is found that the memristance, memcapacitance, and meminductance are caused by different combinations of nonlinear electric responses. The mathematical expressions for the currents through any voltage-driven memristor, memcapacitor, and meminductor are given, and the corresponding expressions for the memristance, memcapacitance, and meminductance are derived. Moreover, a method to determine the charge–flux relationship of a memristor is proposed.

A Novel Design for Memristor-Based Logic Switch and Crossbar Circuits

Abstract: Recently, it has been demonstrated that memristors can be utilized as logic gates, control switches as well as memory elements. In this paper, we analyze the different AND, OR, and NOT logic gates which are based on memristors. In addition, a novel design for a memristor-based switch is presented, which can be used in the peripheral read/write circuits of the memristor-based memory. Moreover, methods of consecutive read with long refresh intervals and fast write for the proposed design are also discussed. Another highlight of this work is the analysis of the proposed memristor-based crossbar architecture which has a series of excellent features, such as good-compatibility, high-density, non-volatility, low-power, and good-scalability. Simulation results also show that the proposed memory array has superior performances compared to other memristor-based arrays proposed in the existing technical literature.

A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology

Abstract: Memristor, the fourth basic circuit element, demonstrates obvious stochastic behaviors in both the static resistance states and the dynamic switching. In this work, a novel memristor-based true random number generator (MTRNG) is presented which leverages the stochastic property when switching a device between its binary states. Compared to conventional random number generators that require amplifiers or comparators with high complexity, the use of memristors significantly reduces the design cost: a basic MTRNG consists of only one memristor, six transistors, and one D Flip-flop. To maximize the entropy of the random bit generation, we further enhanced the design to a 2-branch scheme which can provide a uniform bit distribution. Our simulation results show that the proposed MTRNGs offer high operating speed and low power consumption: the reading clocks of the basic 1-branch and the enhanced 2-branch schemes can reach at 1.05GHz and 0.96GHz with power assumptions of 31.1"W and 80.3"W, respectively. Moreover, the zero-versus-one distributions and sampling rates of MTRNGs can be flexibly reconfigured by modulating the width and amplitude of the programming pulse applied on a memristor and therefore adjusting its switching probability between ON and OFF states.

Ultrahigh Density Memristor Neural Crossbar for On-Chip Supervised Learning

Abstract: Although there are many candidates for future computing systems, memristor-based neural crossbar (NC) is considered especially promising, thanks to their low power consumption, high density, and fault tolerance. However, their implementation is still hindered by the limitations of CMOS neuron and learning cells. In this paper, we present a memristor-based NC that implements on-chip supervised learning. Instead of using a standard CMOS neuron, a simple CMOS inverter realizes the activation function. More importantly, we propose a compact learning cell that consists of a crossbar latch of two antiparallel oriented binary memristors. This design allows for higher density integration and could be naturally extended to a multilayer neural network. Using the CMOS 40-nm design kit and a physics-based compact model of high-performance ferroelectric tunnel memristor, we performed transient simulations to validate the function of the proposed neural crossbar. Then, we construct a multilayer NC by cascading monolayer networks; thereby, enabling the network to learn nonlinearly separable functions (e.g., XOR function). Finally, the fault tolerance is evaluated with Monte Carlo simulation. Analysis of simulation results demonstrates promising applications of our proposed neural crossbar for on-chip supervised learning.

A Novel Nondestructive Read/Write Circuit for Memristor-Based Memory Arrays

Abstract: Emerging nonvolatile universal memory technology is vital for providing the huge storage capabilities, which is needed for nanocomputing facilities. Memristor, which is recently discovered and known as the missing fourth circuit element, is a potential candidate for the next-generation memory. Memristor has received extra attention in the last few years. To support this effort, this paper presents a novel read/write circuit that facilitates the reading and writing operation of the Memristor device as a memory element. The advantages of the proposed read/write circuit are threefold. First, the proposed circuit has a nondestructive successive reading cycle capability. Second, it occupies less die area. Finally, the proposed read/write circuit offers a significant improvement in power consumption and delay time compared with other read/write circuits.

Compensated Readout for High-Density MOS-Gated Memristor Crossbar Array

Abstract: Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.

Improving memristor memory with sneak current sharing

Abstract: Several memory vendors are pursuing different kinds of memory cells that can offer high density, non-volatility, high performance, and high endurance. There are several on-going efforts to architect main memory systems with these new NVMs that can compete with traditional DRAM systems. Each NVM has peculiarities that require new microarchitectures and protocols for memory access. In this work, we focus on memristor technology and the sneak currents inherent in memristor crossbar arrays. A read in state-of-the-art designs requires two consecutive reads; the first measures background sneak currents that can be factored out of the current measurement in the second read. This paper introduces a mechanism to reuse the background sneak current measurement for subsequent reads from the same column, thus introducing "open-column" semantics for memristor array access. We also examine a number of data mapping policies that allow the system to balance parallelism and locality. We conclude that on average, it is better to prioritize locality; our best design yields a 20% improvement in read latency and a 26% memory power reduction, relative to the state-of-the-art memristor baseline.

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors

Abstract: Memristors are being explored for a wide variety of applications such as neuromorphic computing, memory and digital logic. However, they suffer from process variations like any other nanodevice, which in turn impacts their applicability. The effect of process variations, specifically variation in thickness, is highly non-linear on memristors; the effect is greater near the lower memristance region (near M $_{\rm on}$ ) than in the higher memristance region (near M $_{\rm off}$ ). Due to this non-linear effect, many applications do not use the lower memristance values. Consequently, the application's functionality and performance is affected. In this work, we propose a technique called parallel memristors. In this technique, instead of using a single memristor, the application uses several memristors connected in parallel. Each memristor in this parallel structure is programmed to a higher memristance value to tolerate variations. Since many memristors are connected in parallel, the effective memristance value can be near the M $_{\rm on}$ value, thereby achieving high-speed operation. We evaluate the parallel memristor technique in two different applications—memristor-based threshold logic and memristor-based memory. We also perform various optimizations to tradeoff between variation tolerance, power, delay, and area.

Application of the Memristor in Reconfigurable Electromagnetic Devices

Abstract: The recently popularized memristor, short for memory resistor, is investigated in this paper for its potential as a new and attractive method for enabling reconfigurable radio-frequency (RF) devices. The charge- or flux-controlled resistance of this “fourth circuit element” allows for easy reconfigurability and maintains its configured state in the absence of controlling signals. A specialized finite-difference time-domain simulation code is developed and employed to design devices with embedded memristors. The time-domain code allows observation of the nonlinear memristor switching characteristics and real-time functionality of the reconfigurable device. Several different reconfigurable RF devices are designed here to demonstrate the versatility of the memristor and determine the behavior of systems which utilize them.

Modelling of nanostructured TiO2-based memristors

Abstract: The fourth fundamental circuit element memristor completes the missing link between charge and magnetic flux. It consists of the function of the resistor as well as memory in nonlinear fashion. The property of the memristor depends on the magnitude and direction of applied potential. This unique property makes it the primitive building block for many applications such as resistive memories, soft computing, neuromorphic systems and chaotic circuits etc. In this paper we report TiO2-based nanostructured memristor modelling. The present memristor model is constructed in MATLAB environment with consideration of the linear drift model of memristor. The result obtained from the linear drift model is well matched with earlier reported results by other research groups.

The research of memristor-based neural network components operation accuracy in control and communication systems

Abstract: This research is aimed to create a general approach to developing methods and algorithms designed for defining and providing memristor-based artificial neural network (ANNM) components operation accuracy in control and communication systems. Here we list factors which affect the operation accuracy of memristors usied as the synapses in the ANNM. We have created Simscape models of memristor neurons and ANNM for investigating the influence of these factors on the ANNM accuracy. This article presents the results of the initial phase of our research.

Memristor-based linear feedback shift register based on material implication logic

Abstract: Memristor as an emerging history dependent nanometer scaled element will play an important role in future nanoelectronic computing technologies. Some pure and hybrid memristor-based implementation techniques have been proposed in recent years. Material implication logic is one of the significant areas for memristor-based logic implementation. In this paper a memristor-based linear feedback shift register is implemented based on material implication logic. It is implemented by 8 memristors which is considerably used less area in comparison with conventional CMOS-based peers. Also the proposed memristor-based LFSR circuit needs 55 computational steps for generating a 4-bits number.