Showing papers on "Programmable logic array published in 2016"

The Programmable Logic-in-Memory (PLiM) computer

Abstract: Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic circuits, can be economically realized within memristive circuits with a limited performance overhead as compared to the standard computation paradigms. This paper takes a major step along this direction by proposing a fully-programmable in-memory computing system. In particular, we address, for the first time, the question of controlling the in-memory computation, by proposing a lightweight unit managing the operations performed on a memristive array. Assembly-level programming abstraction is achieved by a natively-implemented majority and complement operator. This platform enables diverse sets of applications to be ported with little effort. As a case study, we present a standardized symmetric-key cipher for lightweight security applications. The detailed system design flow and simulation results with accurate device models are reported validating the approach.

A RET-supported logic gate combinatorial library to enable modeling and implementation of intelligent logic functions

Abstract: Boolean logic gates integrate multiple digital inputs into a digital output. Among these, logic gates based on nucleic acids have attracted a great deal of attention due to the prospect of controlling living systems in the way we control electronic computers. Herein, by employing Thioflavin T (ThT) as a signal transducer, we integrated multiple components based on RET (a type of proto-oncogene) into a logic gate combinatorial library, including basic logic gates (NOR, INHIBIT, IMPLICATION), a single three-input NOR gate, and combinatorial gates (INHIBIT–OR, NOT–AND–NOR). In this library, gates were connected in series where the output of the previous gate was the input for the next gate. Subsequently, by taking advantage of the library, some intelligent logic functions were realized. Expectedly, a biocomputing keypad-lock security system was designed by sequential logic operations. Moreover, a parity checker which can identify even numbers and odd numbers from natural numbers was established successfully. This work helps elucidate the design rules by which simple logic can be harnessed to produce diverse and complex calculations by rewiring communication between different gates. Together, our system may serve as a promising proof of principle that demonstrates increased computational complexity by linking multiple logic gates together.

A secure camouflaged threshold voltage defined logic family

Abstract: A myriad of security vulnerabilites can be exposed via the reverse engineering of the integrated circuits contained in electronics systems. The goal of IC reverse engineering is to uncover the functionality and internal structure of the chip via techniques such as depackaging/delayering, high-resolution imaging, probing, and side-channel examination. With this knowledge, an attacker can more efficiently mount various attacks, clone/-counterfeit the design possibly with hardware Trojans inserted, and discover trade secrets. We propose a gate camouflaging technique that relies on the usage of different threshold voltage transistors, but with identical layouts, to determine the logic gate function. In our threshold voltage defined (TVD) camouflaging technique, every TVD logic gate has the same physical structure and is one time mask programmed with different threshold implants for different boolean functionality. We design and implement TVD logic gates in an industrial 65nm bulk CMOS process. Using post-layout extracted simulation, we evaluate the logic style for VLSI overheads (area, power, delay) versus conventional logic, for process variablity robustness, and for various security metrics. Further, we evaluate the macro block overheads for ISCAS benchmark designs under various levels of TVD gate replacement upto and including 100% replacement. TVD logic gates are found to be CMOS process compatible, low overhead, and to increase security against various forms of attacks.

Sub-kBT micro-electromechanical irreversible logic gate.

Abstract: In modern computers, computation is performed by assembling together sets of logic gates. Popular gates like AND, OR and XOR, processing two logic inputs and yielding one logic output, are often addressed as irreversible logic gates, where the sole knowledge of the output logic value is not sufficient to infer the logic value of the two inputs. Such gates are usually believed to be bounded to dissipate a finite minimum amount of energy determined by the input-output information difference. Here we show that this is not necessarily the case, by presenting an experiment where a OR logic gate, realized with a micro-electromechanical cantilever, is operated with energy well below the expected limit, provided the operation is slow enough and frictional phenomena are properly addressed.

Mapping for Maximum Performance on FPGA DSP Blocks

Abstract: The digital signal processing (DSP) blocks on modern field programmable gate arrays (FPGAs) are highly capable and support a variety of different datapath configurations. Unfortunately, inference in synthesis tools can fail to result in circuits that reach maximum DSP block throughput. We have developed a tool that maps graphs of add/sub/mult nodes to DSP blocks on Xilinx FPGAs, ensuring maximum throughput. This is done by delaying scheduling until after the graph has been partitioned onto DSP blocks and scheduled based on their pipeline structure, resulting in a throughput optimized implementation. Our tool prepares equivalent implementations in a variety of other methods, including high-level synthesis (HLS) for comparison. We show that the proposed approach offers an improvement in frequency of 100% over standard pipelined code, and 23% over Vivado HLS synthesis implementation, while retaining code portability, at the cost of a modest increase in logic resource usage.

Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits

Abstract: Layout-level gate camouflaging has attracted interest as a countermeasure against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gates in a circuit are camouflaged, and each camouflaged gate layout can implement a few different logic functions. The security of camouflaging relies on the difficulty of learning the overall combinational logic function without knowing which logic functions the camouflaged gates implement.

Gate-level netlist reverse engineering for hardware security: Control logic register identification

Abstract: The heavy reliance on third-party resources, including third-party IP cores and fabrication foundries, has triggered the security concerns that design backdoors and/or hardware Trojans may be inserted into fabricated chips. While existing reverse engineering tools can help recover netlist from fabricated chips, there is a lack of efficient tools to further analyze the netlist for malicious logic detection and full functionality recovery. While it is relatively easy to identify the functional modules from the netlist using pattern matching methods, the main obstacle is to isolate control logic registers and reverseengineering the control logic. Upon this request, we proposed a topology-based computational method for register categorization. Through this proposed algorithm, we can differentiate data registers from control logic registers such that the control logic can be separated from the datapath. Experimental results showed that the suggested method was capable of identifying control logic registers in circuits with various complexities ranging from the RS232 core to the 8051 microprocessor.

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Abstract: In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits

Abstract: We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors in series. This leads to topological differences and increased flexibility in circuit design. We found that especially complex functions, like Majority and Parity gates of many inputs, which are generally avoided in standard CMOS technology, benefit from the new device type. This can be exploited to directly map reconfigurable building blocks, e.g. dynamically switching NAND to NOR. Exemplary 6-functional logic circuits will be shown, which exhibit up to 80% reduction in transistor count, while maintaining the same functionality as compared to the CMOS reference design. Logical effort analysis indicates that 20% less circuit delay and 33% less normalized dynamic power consumption can be achieved.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Abstract: An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

Multifunctional Graphene/DNA-Based Platform for the Construction of Enzyme-Free Ternary Logic Gates

Abstract: In this work, we have successfully realized multivalued logic circuits including ternary INHIBIT and ternary OR logic gates in an enzyme-free condition by integration of graphene oxide and DNA for the first time. Compared to the binary logic gate with two states of “0” and “1”, the multivalued logic gate contains three different states of “0”, “1”, and “2”, which can increase the information content in a system and further improve the ability of information processing. Such types of multivalued logic operations provide a wider field of vision toward DNA-based algebra logical operations to make applications more accurate with complexity reduction and accelerate the development of advanced logic gates.

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform

Abstract: This article presents the Zynq UltraScale+ MPSoC (multiprocessor system on chip), which builds on the Zynq-7000 family. Compared to the first-generation Zynq, MPSoC increases performance and power efficiency while significantly improving the integration level between the SoC and the field-programmable gate array (FPGA). It also further raises the programming abstraction with the introduction of a new heterogeneous system-wide compiler. At the hardware level, system-wide coherency and shared virtual memory bridge across the processor subsystem into the programmable logic array. The new SDSoC (software-designed SoC) environment combines the ARM compiler with a high-level synthesis technology-based FPGA compiler and a full-system optimizing compiler to target all elements of the heterogeneous SoC from a common program source.

Integration of DNA and graphene oxide for the construction of various advanced logic circuits.

Abstract: Multiple advanced logic circuits including the full-adder, full-subtract and majority logic gate have been successfully realized on a DNA/GO platform for the first time. All the logic gates were implemented in an enzyme-free condition. The investigation provides a wider field of vision towards prototypical DNA-based algebra logical operations and promotes the development of advanced logic circuits.

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Abstract: Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 $\times$ 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.

A knowledge-based programmable logic controller with flexible in-field knowledge management and analytics

Abstract: A method of operating an intelligent programmable logic controller over a plurality of scan cycles includes the intelligent programmable logic controller executing a control program and one or more reasoning algorithms for analyzing data received and transmitted by the intelligent programmable logic controller. The intelligent programmable logic controller receives one or more user-specified declarative knowledge models from an external source via a deployment interface included in the intelligent programmable logic controller. The intelligent programmable logic controller dynamically modifies the reasoning algorithms during runtime of the control program based on the user-specified declarative knowledge models.

High Speed True Random Number Generator Based on FPGA

Abstract: TRN (True Random Number) plays a key role in the communication system and so on. The TRNG (True Random Number Generator) based on FPGA (Field Programmable Gate Array) usually has a high speed and quality. In this article, we study several existing ways to generate the TRN in the FPGA using the oscillator rings which consist of an odd number of NOT gates, the structure of the oscillator rings and the sampling frequency are analyzed. An improved structure based on the oscillator rings is introduced here by which we can get higher speed and quality TRNG with fewer resources compared with the several methods mentioned in the references. The TRNG consists of 16 oscillator rings, each contains 3 NOT gates. The sampling frequency can reach 300M (Million bits per second). The design is implemented on the Altera Stratix II FPGA. The results passed the tests of the NIST (National Institute of Standards and Technology) randomness test suite. The restart experiments have shown that the TRNG outputs behaved truly random and not pseudorandom.

Boolean logic gate exploration for memristor crossbar

Abstract: Emerging technologies are under research as alternatives for next-generation VLSI circuits. One of the promising candidates is memristor due to its scalability, high integration density, non-volatility, etc. Different design styles of memristor-based logic circuits have been proposed. This paper first overviews these design styles and compares them using several criteria. Subsequently, it selects a promising candidate to explore its potential logic gate space. Thereafter, it derives control voltage constraints used to ensure correct logic gate functionality. The newly obtained logic gates are verified by SPICE simulations, and finally the performance of the memristor gates are compared with CMOS gates. The results show that the memristor gates, with reasonable technology improvements, are comparable to CMOS gates or even outperform them.

Multiple perspectives on the hardware implementations of biological neuron models and programmable design aspects

Abstract: A few individual design examples of programmable device-based biological neuron model implementations are available in the literature, but there is no comprehensive study that examines analog and digital programmable design examples of frequently studied biological neuron model implementations. The aim of this paper is to present a comparative study about programmable and recongurable implementations of the FitzHugh{Nagumo, Izhikevich, and Hindmarsh{Rose neuron models. Sinceeld programmable analog array (FPAA) andeld programmable gate array (FPGA) devices offer several advantages such as exible design possibilities, reduction of the complexity of design, real-time modication, and software control for programmable and recongurable implementations of neuron models and neural structures, they are preferred in these implementations as analog and digital programmable devices. Experimental results agree with the numerical simulations and verify the design effectiveness of FPAA- and FPGA-based implementations.

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Abstract: An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (∼30%) to satisfy 10 year retention at 105° C.

Logic-in-Memory With a Nonvolatile Programmable Metallization Cell

Abstract: This paper introduces two new cells for logic-in-memory (LiM) operation. The first novelty of these cells is the resistive random access memory configuration that utilizes a programmable metallization cell as nonvolatile element. CMOS transistors and ambipolar transistors are used as processing and control elements for the logic operations of the LiM cells. The first cell employs ambipolar transistors and CMOS in its logic circuit (7T2A1P), while the second LiM cell uses only MOSFETs (9T1P) to implement logic functions, such as AND, OR, and XOR. The operational mode of the proposed cells is voltage-based, which is much different from the previous designs in which a LiM cell operates on a current mode. Extensive simulation results using HSPICE are provided for the evaluation of these cells; comparison shows that the proposed two cells outperform previous LiM cells in metrics, such as logic operation delays, power delay product, circuit complexity, write time, and output swing.

SoC-FPGA embedded system for real-time thermal image processing

Abstract: The article presents custom digital processing system design with use of state-of-the-art SoC-FPGA technology using ARM Coretex-A9 dual core processor embedded in Altera Programmable Logic Array. In article a discussion is conducted about possibilities of using custom programmable logic architecture alongside with hard-core processor system for real-time image processing adopted to dual-channel radiometric thermal image processing system. Details about hardware-software engineering, driver design for Linux operating system, application engineering and design considerations in highly customisable environment based on Altera SoC-FPGA is presented.

A flexible inexact TMR technique for SRAM-based FPGAs

Abstract: Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area. Moreover, the inexact methods used in ASICs to overcome this problem are not efficient when applied in FPGAs. Therefore, this paper proposes a novel technique based on heuristic to tolerate faults in SRAM-based FPGAs by using inexact modules in conjunction with TMR, thus reducing the area and power overhead of the design. Experiments run on various MCNC benchmark circuits show the accuracy of the proposed technique. They also show that the design solutions found through this technique only differ 0.52% on average from the optimal ones and savings up to 84.4% in terms of computation time can be reached on average.

Hybrid LUT/Multiplexer FPGA Logic Architectures

Abstract: Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VTR and CHStone) using a custom tool flow consisting of LegUp-HLS, Odin-II front-end synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and architecture exploration. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Experimentally, we show that for nonfracturable architectures, without any mapper optimizations, we naturally save up to $\sim 8$ % area postplace and route; both accounting for complex logic block and routing area while maintaining mapping depth. With architecture-aware technology mapper optimizations in ABC, additional area is saved, post-place-and-route. For fracturable architectures, experiments show that only marginal gains are seen after place-and-route up to $\sim 2$ %. For both nonfracturable and fracturable architectures, we see minimal impact on timing performance for the architectures with best area-efficiency.

Programmable code fingerprint

Abstract: A method, computer program product, and system performing a method that includes a processor compiling a description including information to be utilized by programmable logic to recognize a code fingerprint in a program executing in the runtime environment. The method also includes the processor configuring the programmable logic, by loading the description into the programmable logic at a predefined time and obtaining, during runtime of the program, an alert that the programmable logic recognized the code fingerprint in the program.

Programmable MISR modules for logic BIST based VLSI testing

Abstract: This paper focus on the design of Programmable MISR(Multiple Input Signature Register) modules for Logic BIST based Very Large Scale Integration(VLSI) Integrated Circuit(IC) testing. The advancement in VLSI technology have made chip testing more complicated which has lead to the popularity of Logic Built In Self Test(LBIST) compared to Automatic Test Equipment(ATE). Logic BIST allows in-built chip testing with the help of an additional hardware structure inside the circuit. The test patterns are not applied by ATE but are generated by inbuilt testing circuits. MISR is commonly used as an output response analyzer since it is alternative to n-parallel LFSRs. MISRs accelerates the testing methodology by compacting multi-bit streams into single signature. A Reconfigurable LFSR can be used as the test pattern generator as well as a response compactor inside Logic BIST to improve the fault coverage of IC testing. The proposed MISR architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 64) programmable MISR structures is synthesized in Xilinx Spartan 6 for implementing MISR on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete MISR are implemented. All the designs are synthesized for ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable designs are analyzed for speed, power and area.

Accelerating Particle Filter on FPGA

Abstract: Particle filters (PFs) are Bayesian based estimationalgorithms with attractive theoretical properties for addressingwide range of complex applications that are nonlinear and nonGaussian. However, they are associated with a huge computational demand which limited their application in most realtime systems. To address such a drawback in PFs, this paperpresents different approaches for PFs acceleration based on afield programmable gate arrays (FPGAs).