Showing papers on "Snapback published in 2019"

Reverse-Conducting Insulated Gate Bipolar Transistor: A Review of Current Technologies

Abstract: The reverse-conducting insulated gate bipolar transistor (RC-IGBT) has several benefits over a separate IGBT and diode solution and has the potential to become the dominant device within many power electronic applications; including, but not limited to, motor control, resonant converters, and switch-mode power supplies. However, the device inherently suffers from many undesirable design tradeoffs which have prevented its widespread use. One of the most critical issues is the snapback seen in the forward conduction characteristic which can prevent full turn-on of the device and result in the device becoming unsuitable for parallel operation (required in many high voltage modules). This phenomenon can be suppressed but at the expense of the reverse conduction performance. This paper provides an overview of the technical design challenges presented by the RC-IGBT structure and reviews alternative device concepts which have been proposed in literature. Analysis shows that these alternate concepts either present a tradeoff in performance characteristics, an inability to be manufactured, or a requirement for a custom gate drive.

Analysis of the Novel Snapback-Free LIGBT With Fast-Switching and Improved Latch-Up Immunity by TCAD Simulation

Abstract: In this letter, a novel snapback-free LIGBT with fast-switching and improved latch-up immunity is proposed and investigated by TCAD simulation. The structure features a shorted-anode NPN (SA NPN) beside the insulated oxide trench in the N-buffer and a lowly doped P-region (PD) alongside the deep-oxide trench (DOT) in the N-drift. The SA NPN provides an effective path of electron extraction and completely suppresses the snapback voltage. The PD changes the transmission path of hole current, makes the distribution of hole current more uniform, and contributes to the depletion of the drift region. As simulation results show, at the same forward voltage drop of 1.40 V, the turn-off time for the proposed SAPD LIGBT is reduced by 36.6% and 57.4%, respectively, compared with SA LIGBT and DOT LIGBT. In addition, compared with DOT LIGBT, breakdown voltage is increased by 7.6% and latch-up voltage is increased by nearly 20% for the proposed SAPD LIGBT.

ESD Reliability of AlGaN/GaN HEMT Technology

Abstract: This experimental study reports new aspects of electrostatic discharge (ESD) behavior in AlGaN/GaN HEMTs. The role of Schottky gate and MESA is investigated using special test structures. Influence of piezoelectric field, carrier trapping, and self-heating on ESD behavior is studied. A unique power-law-like behavior is found. Linear scaling of failure current with source–drain spacing is reported. Spot measured drain-to-source DC current is realized as an important parameter to monitor degradation. Unique degradation trends are observed for the first time and a correlation between snapback depth and % degradation is established. Cumulative nature of device degradation is discovered. Change from soft to hard failure with an increase in pulsewidth (PW) is reported. Finally, the cause of snapback instability observed in device, at low PW, is discussed.

Novel Silicon-Controlled Rectifier With Snapback-Free Performance for High-Voltage and Robust ESD Protection

Abstract: A novel snapback-free silicon-controlled rectifier (SFSCR) with P-type Zener implantation (ZP) is developed in a 0.5- $\mu \text{m}$ bipolar CMOS DMOS technology for latch-up immune high-voltage (HV) electrostatic discharge (ESD) protection. The inherent snapback of SCR is successfully suppressed by the novel ZP technique. But, it also brings about a serious degradation in failure current ( ${I}_{\textsf {t2}}$ ) when compared with the regular low holding voltage ( ${V}_{h}$ ) device. In order to mitigate such degradation, a novel layout terminal is proposed. According to the transmission-line pulse test results, ${I}_{\textsf {t2}}$ of the SFSCR with new layout is increased by 58.5%, while the ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) is reduced by 48.7% under the same layout area. By comprehensive comparison, the SFSCR is proved to be a potential HV ESD solution.

Analysis of the Fast-Switching LIGBT With Double Gates and Integrated Schottky Barrier Diode

Abstract: A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity.

TVS Devices Transient Behavior Modeling Framework and Application to SEED

Abstract: The transient behavior for four different types of TVS (non-snapback, snapback, spark gap, varistor) is modeled using the same modeling framework. By a 10 ns VF-TLP, the quasi-static I-V curve and the transient turn-on are captured and modeled in ADS. The models are applied in a SEED simulation to investigate the strengths and weaknesses of the modeling frame.

A Snapback-Free and Low Turn-Off Loss Reverse-Conducting SOI-LIGBT With Embedded Diode and MOSFET

Abstract: A novel snapback-free and low turn-off loss reverse-conducting (RC) SOI-LIGBT is proposed and investigated by numerical simulations. An n-MOSFET (MN2) is embedded in the anode side of the LIGBT to short the P-anode/N-buffer junction during the turn-off transient, thus allowing the LIGBT to be turned off rapidly without excessive tail current. In addition, MN2 enable the LIGBT to conduct the reverse conducting current like the freewheeling diode. In the forward-conducting state, MN2 is turned off, then the proposed LIGBT operates like a conventional one and the snap-back is avoided. The gate electrode of MN2 can be controlled synchronously by the gate signal of the LIGBT which is level-shifted by a p-i-n diode (D1) and processed by an anode-controlling circuit, and therefore, the proposed RC-LIGBT still maintains a three-terminal configuration. D1 and MN2 are embedded in the drift region and anode-side of the LIGBT, respectively, and they can be isolated by deep-oxide trenches. The numerical simulation results reveal that the turn-off loss ( ${E} _{\mathrm{ off}}$ ) and reverse recovery charge of the proposed LIGBT is reduced by 58.3% and 38.9%, respectively, compared with the conventional LIGBT combining with antiparallel freewheeling diode.

Simulation Study of a Novel Full Turn-On RC-IGBT With Ultralow Energy Loss

Abstract: A novel full turn-on RC-IGBT with ultralow energy loss is proposed and investigated by simulations. It features a “collector-side” semi-superjunction (CSJ) and a shorted collector trench (SCT). First, the SCT combined with the CSJ can stop and optimize the electric field without the N-buffer layer in the forward blocking state, leading to an optimized trade-off between breakdown voltage and forward voltage drop. Second, because of the lateral depletion region in the CSJ, the parasitic P-base/N-drift/P-pillar/ N-shorted thyristor can be triggered easily, enabling the novel IGBT to conduct reverse current. Third, due to the electron barrier set by the SCT and the CSJ, electron carriers are stored near the P-collector/N-pillar junction until it turns on. Consequently, the proposed RC-IGBT can eliminate the snapback effect completely in the forward conduction state. The simulation results show that, when compared with the FPL RC-IGBT, the proposed RC-IGBT delivers a comparable blocking capability while featuring full turn-on capability and a 25% forward voltage drop reduction, resulting in ultralow energy loss.

Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability

Abstract: A unique low current ESD failure during snapback region, which otherwise survive high current stress, is reported in LDMOS-SCR device. The failure is universal to LDMOS-SCR devices designed as self-protected MOS switch and found to be specific to a window of current between trigger and holding state, which can only be captured using high resistance load-line in TLP system. This resulted in severe power scalability issues in LDMOS-SCRs. In this work, while using systematic experiments and 3D TCAD simulations, we have developed detailed physical insights into the unique low current ESD failure phenomenon in LDMOS-SCR devices.

Compact Modeling of Complementary Resistive Switching Devices Using Memdiodes

Abstract: In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach.

Investigation of the Dual Implant Reverse-Conducting SuperJunction Insulated-Gate Bipolar Transistor

Abstract: This letter presents the dual implant superjunction (SJ) trench reverse-conducting (RC) insulated-gate bipolar transistor (IGBT) concept with two implanted SJ pillars in the drift region: one from the cathode side and another from the anode side. The proposed device is compatible with current manufacturing processes and enables a full SJ structure to be achieved in a 1.2-kV device, as alignment between the pillars is not required. Extensive technology computer aided design (TCAD) simulations have been performed and demonstrated that utilizing this dual implantation technique can result in a 77% reduction in turn-off losses for the full SJ structure, compared to a conventional RC-IGBT. The results show that any snapback in the ON-state waveform significantly increases the turn-off losses and only a deep SJ device (pillar $\text {gap} ) warrants the additional processing expense.

Fast-Switching Lateral IGBT with Trench/Planar Gate and Integrated Schottky Barrier Diode (SBD)

Abstract: A novel fast-switching lateral IGBT with trench/planar gate and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. The proposed LIGBT consists of the trench/planar gate (TP) at the cathode and an integrated SBD at the anode to reduce turn-off time and maintain a low forward voltage drop. The integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. The insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. The simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of the proposed LIGBT. Moreover, the latch current density of the proposed LIGBT is increased by nearly 200% compared to that of the conventional LIGBT which means that the proposed LIGBT can improve the latch immunity.

A new snapback-free base resistance controlled thyristor with semi-superjunction

Abstract: A base resistance controlled thyristor with semi-superjunction (Semi-SJ BRT) is proposed in this paper. The highly doped P-pillar in drift region extracts injected holes into thyristor, then hole current density in thyristor will be improved and parasitic transistor is significantly suppressed. Meanwhile, highly doped drift region reduces drift resistance, then thyristor trigger current is enhanced. Snapback is greatly suppressed. In addition, much more minority carriers will be extracted due to charge coupling effect in drift region. Turn-off loss is reduced and trade-off performance is improved. Numerical simulation results show that, when the pillar doping level is higher than 1.0 × 1015 cm−3, snapback-free can be realized and turn-off loss can be reduced by 22.28%.

Measurement based accurate definition of the SOA edges for SiGe HBTs

Abstract: This paper presents a non-destructive method to characterize the SiGe HBTs (heterojunction bipolar transistors) at very high currents/voltages, close to the functional boundaries of the transistor operation. Based on this measurement, a focus is made at high currents where the snapback behavior is observed using IC/VBE measurement setup. This analysis has been carried out for different transistor geometries. The first and second snapback locus in the IC-VCB characteristic has been discussed. A comparison of the measurements with the HICUM model shows accurate simulation results close to and even beyond the second flyback locus.

Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors

Abstract: The boundaries that determine the LDMOS transient safe operating area are presented. It includes the time-independent electrical SOA (eSOA) and short-pulse transient SOA post device snapback. A compact modeling methodology is introduced for high voltage LDMOS with minimal circuit simulation convergence shortcomings. By adding a failure monitor, the model proposed can be used to determine both the boundaries of eSOA and short-pulse transient SOA.

A Snapback-Free Reverse-Conducting IGBT with Integrated Schottky Diode in the Collector

Abstract: A novel snapback-free reverse-conducting insulated gate bipolar transistor with integrated schottky diode in the collector (ISD-RC-IGBT) is proposed. The proposed structure features an ISD between the n+collector and the n field stop (FS) layer in the device bottom. The simulation results show that compared to the conventional RC-IGBT, the proposed device demonstrates excellent overall performance in both IGBT and diode modes. Meanwhile, the device reliability is also improved owing to the uniform carriers and current distribution in the drift region in both IGBT and diode modes.

Modeling and Simulation of Diode Triggered Silicon Controlled Rectifier Behavior under ESD Stresses

Abstract: A Diode Triggered Silicon Controlled Rectifier (DTSCR) is modeled. This DTSCR compact model is able to simulate the DTSCR’s I-V characteristics with snapback. Overshoot related parameters in this model also reproduces the overshoot phenomenon in transient simulation. Simulation of non-linear resistivity in the high current region is modeled based on the electro-thermal behavior and velocity saturation. This model is not only able to simulate quasi-static I-V under typical ESD stresses, but can predict ESD failure with arbitrary input ESD waveforms.

A Snapback-free RC-IGBT with Si 3 N 4 Trench and P-type Pillar

Abstract: A novel structure of reverse conduction insulated gate bipolar transistor (RC-IGBT), which can be applied to 1200V IGBT modules, has been proposed. It features a Si 3 N 4 trench placed between the n-collector, the p-collector and a p-pillar upon the Si 3 N 4 trench. The novel structure introduces a high-resistance collector short resistor at low current density, which leads to the suppression of the snapback effect. The collector short resistance can be adjusted by varying the length, width and concentration of the p-pillar without increasing the collector cell length. The simulation results show that the proposed novel structure can eliminate the voltage snapback effect and has a better relationship with the forward voltage drop and the turn-off loss of IGBT devices.

A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant

Abstract: A novel high voltage NPN (HV-NPN) device with buried floating P-type (BFP) implant at collector side was developed for electrostatic discharge (ESD) protection in a 130nm low cost high voltage CMOS technology. The characteristics of the novel HV-NPN device using transmission line pulse (TLP) measurements show that a second snapback enhances the failure current and reduces the on-resistance at a certain high current levels. The device mechanism is illustrated with technology computer aided design (TCAD)s imulation results.

Snapback-free base resistance controlled thyristor with floating N-region

Abstract: An analysis model of snapback voltage for the base resistance controlled thyristor (BRT) is developed in this paper. It’s shown that, improving hole current flowing into P-base region is an important way to suppress snapback phenomenon during forward conducting state. Thus, a new BRTwith a floating N-region in N-drift layer is proposed. In this new structure, the floating N-region introduces a hole potential barrier in parasitic PNP to prevent holes from being swept into cathode. Then, almost all of hole current flow into P-base to trigger latch-up effect and the parasitic PNP transistor is greatly suppressed. Thus, snapback is significantly suppressed. Numerical simulation results show that, when doping level and length of floating N-region are 8.0 × 1015 cm−3 and 5.0 μm, snapback-free can be realized, and pulse discharge performance and turn on characteristics are greatly improved meanwhile the high blocking capability is maintained.

Reverse-conducting trench insulated gate bipolar transistor

Abstract: The invention discloses a reverse-conducting trench insulated gate bipolar transistor, and belongs to the technical field of semiconductor devices. Compared with a traditional reverse-conducting trench insulated gate bipolar transistor (IGBT) structure, a collector side part superjunction structure and a collector short-circuit trench structure are arranged at a collector side, and meanwhile, an N-buffer layer structure is removed; under a reverse-conducting state, a P-column generates a punch-through effect by transverse exhaustion of a collector side part superjunction, and an NPNP transistor is triggered to be started so as to achieve reverse conduction; and under positive conduction, a potential barrier layer is formed by transverse diffusion of the collector side part superjunction, the collector short-circuit groove structure is used as a dielectric barrier layer, electrons are stored in a part near to a P-collection region/N-column by a joint effect of the collector side part superjunction structure and the collector short-circuit trench structure until a PN junction is conducted, and a snapback phenomenon is greatly suppressed. Meanwhile, the area of the P-collection area is effectively utilized, and the conduction voltage drop is reduced. The reverse-conducting IGBT has the beneficial effects that the snapback phenomenon is effectively suppressed on the premise of no obvious influence on other performance of the device, and low-power loss is obtained.

Reverse-conducting IGBT with superjunction

Abstract: The invention relates to a power semiconductor technology, in particular, to a reverse-conducting IGBT with a superjunction. In comparison with the traditional superjunction reverse-conducting IGBT, one part of P+ collector regions in collector regions is replaced by N+ collector regions; an N-type drift region is divided to two disconnected N-type drift regions by using a P-type strip and a dielectric isolation layer; the P+ collector region and the N+ collector region are located in respective N-type drift regions; in the case of forward conduction of the device, as the left N-type drift region and the right N-type drift region are isolated oppositely, the conduction state approximates the superposition of the left IGBT bipolar conduction state and the right MOS monopole conduction statewith no snapback phenomenon. Due to the existence of the N+ collector region, the device can achieve reverse conduction. The reverse-conducting IGBT with a superjunction has the beneficial effects that the reverse-conducting capability is realized, no snapback phenomenon exists, and the current distribution during reverse conduction is optimized.

TVS (Transient Voltage Suppressor) device with low residual voltage, high surge and one-way snapback and manufacturing method thereof

Abstract: The invention discloses a TVS (Transient Voltage Suppressor) device with low residual voltage, high surge and one-way snapback and a manufacturing method thereof. The device comprises an N-type substrate, and is characterized in that a P-type epitaxial layer is arranged on the N-type substrate, the P-type epitaxial layer is provided with an SN layer and an SP layer, the SN layer and the SP layer are isolated by a deep trench. The device provided by the invention not only reduces the breakdown voltage, but also greatly improves the peak current IPP in the breakdown direction while providing lowleakage current. Meanwhile, the device reduces the clamping voltage in the positive conduction direction and the negative breakdown direction, so that the protected device is completely located in asafe area. The device has the advantages of high power, low cost and the like.

A Snapback Suppressed Base Resistance Controlled Thyristor with Double N-type Buried Layer

Abstract: A new base resistance controlled thyristor with double N-type buried layer (DNBL-BRT) is proposed in this paper. In the new structure, the left N-buried layer introduces an electron potential trap to extract electron current into thyristor, then effective thyristor trigger current is enhanced. Meanwhile, the right N-buried layer acts as a hole potential barrier to push hole current into P-base region, then parasitic PNP is suppressed and hole current density in P-base region is improved. Snapback phenomenon is significantly suppressed. Numerical simulation results show that, snapback-free can be realized when the doping level of N-buried layers is $1.0 \times 10^{15}$ $\mathrm{c m}^{-3}$and the distance between the two N-buried layers is 1.5 $\mu$m, meanwhile high blocking capability is maintained.

Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs

Abstract: Carrier generation due to impact ionization is an underlying physical mechanism in the snapback phenomenon. An exceedingly large amount of current during the snapback phenomenon is supplied from the two branches of carrier generation due to impact ionization; one originates from the surface channel current and the other from the source-junction injected current which tends to flow across a deeper location than the surface channel current. Device simulation for a power Laterally-Diffused MOSFET has revealed twin peaks of carrier generation rate distribution near the drain junction. This finding validates an incorporation of substrate current model equations in a common functional form to a MOSFET compact model, except for a distinct set of model parameters respectively; one for the shallow current and the other for the deep current.

A Novel Snapback-Free Reverse-Conducting (RC) SOI-LIGBT with a Built-in Thyristor

Abstract: A novel reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed. It features a built-in thyristor formed by introducing a floating P-well surrounding an N+ collector. The realization of the thyristor barely increases chip area or complicates fabrication. It helps to realize the RC function and prevents the device from working in the unipolar mode, which eliminates the snapback problem. Moreover, since the thyristor provides an electron extraction path during the turn-off operation, the switching performance is improved. Simulation results show that, compared with the conventional LIGBT with an antiparallel diode, the proposed device presents the reverse recovery charge (Qrr) and the turn-off loss (Eoff) reduced by more than 30%, and the RC voltage drop (VF) decreased by about 0.1V.

Super-junction LIGBT power device

Abstract: The invention relates to a super-junction LIGBT power device, and belongs to the technical field of semiconductor power devices. A doped layer of a second conductive type is introduced into an anode resistance region of a transverse IGBT, so as to control the flowing path of the current in the anode resistance area and to control the voltage drop of the anode resistance region; therefore, the snapback phenomenon of the LIGBT can be inhibited, and the manufacturing difficulty of the process is not increased through the structure of accurately controlling the resistance value of the anode resistance region, so that the snapback phenomenon of the LIGBT can be accurately inhibited on the basis of not changing the process.