Showing papers on "Spice published in 2013"

Generalized Memristive Device SPICE Model and its Application in Circuit Design

Abstract: This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

SPICE – Simulation Program with Integrated Circuit Emphasis

Abstract: SPICE est un logiciel qui m’a beaucoup émerveillé lorsque j’étais étudiant, de par sa puissance et sa simplicité d’utilisation. Il est vrai que nous faisions beaucoup de travaux pratiques en électronique, et le simple fait de pouvoir mettre son circuit sous forme de liste, appelée netlist, et de le simuler était une découverte fascinante. SPICE a servi de modèle à nombre d’autres programmes de simulation, dans les universités et dans l’industrie, grâce à son modèle précoce Open Source. Aujourd’hui toute l’électronique se concentre sur une puce, et les logiciels de simulation utilisés sont plutôt du type VHDL [1], voire mixte continu/événementiel [2], mais dont la plupart sont inspirés de SPICE. Actuellement, on édite de manière graphique son schéma et on lance directement la simulation depuis son interface graphique. Ce qu’il faut savoir c’est que bon nombre de ces interfaces graphiques construisent une netlist et c’est un SPICE adapté qui fera la simulation par-derrière. La première version de SPICE date de 1972 et a été écrite en fortran, rapidement suivie par la deuxième version en 1975. Il faudra attendre 1989 pour voir la troisième version (définitive) de SPICE, écrite en C. Il est remarquable d’observer que la troisième version fût la dernière, avec des mises à jour mineures et qui se déclinent en lettre, la dernière étant 3f5. Aujourd’hui, et dans cet article, on utilisera Ngspice [3] qui est basé sur la dernière version de SPICE, et qui se trouve sous licence GNU GPL2. Il est fourni par le groupe de développement gEDA [4] qui a repris le flambeau pour le développement de tous les logiciels de simulation ou de conception de circuits électroniques.

Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time

Abstract: This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

Physics-Based SPICE-Compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits

Abstract: A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau-Lifshitz-Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-in-built voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (Ku), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density (JC), switching time (TSWITCH), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators.

A Note on the SPICE Method

Abstract: In this article, we analyze the SPICE method developed in , and establish its connections with other standard sparse estimation methods such as the Lasso and the LAD-Lasso. This result positions SPICE as a computationally efficient technique for the calculation of Lasso-type estimators. Conversely, this connection is very useful for establishing the asymptotic properties of SPICE under several problem scenarios and for suggesting suitable modifications in cases where the naive version of SPICE would not work.

A Compact a-IGZO TFT Model Based on MOSFET SPICE ${\rm Level}=3$ Template for Analog/RF Circuit Designs

Abstract: This letter presents a compact model for flexible analog/RF circuits design with amorphous indium-gallium-zinc oxide thin-film transistors (TFTs). The model is based on the MOSFET LEVEL=3 SPICE model template, where parameters are fitted to measurements for both dc and ac characteristics. The proposed TFT compact model shows good scalability of the drain current for device channel lengths ranging from 50 to 3.6 μm. The compact model is validated by comparing measurements and simulations of various TFT amplifier circuits. These include a two-stage cascode amplifier showing 10 dB of voltage gain and 2.9 MHz of bandwidth.

A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation

Abstract: This paper presents a SPICE compatible model of a dual-gate bilayer graphene field-effect transistor. The model describes the functionality of the transistor in all the regions of operation for both hole and electron conduction. We present closed-form analytical equations that define the boundary points between the regions to ensure Jacobian continuity for efficient circuit simulator implementation. A saturation displacement current is proposed to model the drain current when the channel becomes ambipolar. The model proposes a quantum capacitance that varies with the surface potential. The model has been implemented in Berkeley SPICE-3, and it shows a good agreement against experimental data with the normalized root-mean-square error less than $10\%$ .

THz SPICE for Modeling Detectors and Nonquadratic Response at Large Input Signal

Abstract: The THz SPICE model is capable of simulating field effect transistors (FETs) in a plasmonic mode of operation at frequencies far above the device cutoff frequency. The model uses a distributed RC or RLC network and is validated by comparison of the simulation results with our analytical model of the plasmonic detector, and with measured results. It also allows us to determine the operation regimes, where conventional SPICE models are still applicable. The applicability of this model for THz sensing applications is demonstrated by simulating the plasmonic THz FET sensor with on-chip amplifier.

Modeling Terahertz Plasmonic Si FETs With SPICE

Abstract: As operating frequencies of Si FETs continue to grow, commercial circuit modeling tools must provide accurate simulations at very high frequencies with the ability to model plasmonic FETs in large and complex circuits. Traditional compact SPICE models used by commercial CAD tools model the channel resistance and capacitance and gate resistance as single lumped elements or use approximations to model the distributed nature of the FET channel. At high frequencies, these models become inaccurate and fail to model device physics properly. To describe plasmonic FETs, a THz SPICE model is developed for Si FETs. The THz SPICE model is validated experimentally to be in close agreement with measured results. The model is used to show predicted device response at different technology nodes.

Realization of first-order current-mode filters with low number of mos transistors

Abstract: In this paper, a new current-mode (CM) circuit for realizing all of the first-order filter responses is suggested. The proposed configuration contains low number of components, only two NMOS transistors both operating in saturation region, two capacitors and two resistors. Major advantages of the presented circuit are low voltage, low noise and high linearity. The proposed filter circuit can simultaneously provide both inverting and non-inverting first-order low-pass, high-pass and all-pass filter responses. Computer simulation results achieved through SPICE tool and experimental results are given as examples to demonstrate performance and effectiveness of the proposed topology.

Improved SPICE electrical model of silicon photomultipliers

Abstract: The present work introduces an improved SPICE equivalent electrical model of silicon photomultiplier (SiPM) detectors, in order to simulate and predict their transient response to avalanche triggering events. In particular, the developed circuit model provides a careful investigation of the magnitude and timing of the read-out signals and can therefore be exploited to perform reliable circuit-level simulations. The adopted modeling approach is strictly related to the physics of each basic microcell constituting the SiPM device, and allows the avalanche timing as well as the photodiode current and voltage to be accurately simulated. Predictive capabilities of the proposed model are demonstrated by means of experimental measurements on a real SiPM detector. Simulated and measured pulses are found to be in good agreement with the expected results.

VDDDA - New ‘voltage differencing’ device for analog signal processing

Abstract: This paper presents a new `voltage differencing' active building block called voltage differencing differential difference amplifier (VDDDA). The usefulness of the introduced device is demonstrated on novel resistorless voltage-mode first-order all-pass filter and voltage-mode quadrature oscillator design. The pole frequency of the filter can be easily controlled by means of internal transconductance and it provides both high-input and low-output impedances, which is important for cascading. In the oscillator the condition of oscillation and frequency of oscillation can be tuned independently. The theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 SCN018 CMOS process parameters with ±0.9 V supply voltages.

Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA

Abstract: This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

Single-Input Four-Output Current Mode Filter Using Operational Floating Current Conveyor

Abstract: This paper presents operational floating current conveyor (OFCC) based single input four output current mode filter. It employs only three OFCCs and two grounded capacitors and resistors each. The MOS based grounded resistors implementation is used, which adds feature of electronic tunability to the filter parameters. The filter also enjoys low component spread and low sensitivity performance. The effect of finite transimpedance and parasites of OFCC on the proposed circuit is also analyzed. The functionality of the proposed circuit is demonstrated through SPICE simulations using 0.5 µm CMOS process model provided by MOSIS (AGILENT).

BSIM compact MOSFET models for SPICE simulation

Abstract: Continuous technology advancements have forced MOSFET architecture to evolve from bulk to SOI to multigate MOSFETs. BSIM compact models have helped circuit designers to realize their designs first time correct using accurate physical models used in SPICE simulation. BSIM3 and BSIM4 are threshold voltage based bulk MOSFET models while BSIM6 is charge based bulk MOSFET model, which include physical effects such as mobility degradation, current saturation, high frequency models etc. BSIM6 has been developed especially to address symmetry around Vds = 0, thus providing smooth higher order derivatives. BSIM-CMG is a CMC standard surface potential based model for common symmetric double, triple, quadruple and surround gate (nanowire) MOSFETs. Long channel DIBL also called Drain-Induced Threshold Shift (DITS) effect and asymmetric charge weighing factor etc. have been recently included in it. BSIM-IMG is a surface potential based model to simulate ultra-thin body devices such as UTBSOI but also other thin body devices such as MOS2 transistor.

A compact SPICE model for statistical post-breakdown gate current increase due to TDDB

Abstract: We developed a compact SPICE model capable of modeling the increases in post-breakdown (BD) gate current (IG_BD) due to time-dependent dielectric breakdown (TDDB), for circuit level simulations. IG_BD is determined by the random shape of the BD path given by the percolation model and the location of BD path. The statistical nature of our analysis provides different IG_BD for each transistor and hence, can be efficient for statistical circuit simulation. The generated gate current is fed into the proposed SPICE model incorporating transistor threshold voltage shift (VTH-SHIFT) due to bias temperature instability (BTI). We present simulation results of a ring oscillator using our model and compare the results to experimental data from an ultrathin CMOS technology. We also show that IDDQ is a more representative signature of TDDB degradation than the delay of a ring oscillator.

A Physical and SPICE Mobility Degradation Analysis for NBTI

Abstract: The importance of mobility degradation (Δμeff) due to Negative Bias Temperature Instability (NBTI) stress is studied for precise modeling of p-MOSFET drain current degradation (ΔID) An improvement to the SPICE mobility model is presented to incorporate Δμeff , and the modified model is validated against experimental ΔID and transconductance degradation (Δgm) over time, in the subthreshold to strong inversion region, across different SiON and high-k metal gate (HKMG) devices To gain further insight into NBTI mobility degradation, the well-known physics-based mobility model consisting of three scattering components is revalidated across different devices This analysis is beneficial for device and circuit simulations in Technology CAD and SPICE environments, respectively, for different process technologies

Why‐ and how‐ to integrate Verilog‐A compact models in SPICE simulators

Abstract: SUMMARY This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.

Parameter Extraction and Evaluation of UOTFT Model for Organic Thin-Film Transistor Circuit Design

Abstract: In this paper, we report a systematic approach to extract parameters from organic thin film transistors (OTFTs) that are used for compact Spice models. The universal organic thin-film transistor (UOTFT) model and Silvaco's Smartspice platform are utilized for simulations whereas experimental data are collected from Plastic Logic's (PL) thin-film transistors that are processed on flexible plastic substrates. The parameter extraction procedure is outlined where both current-voltage and capacitance-voltage measurements are employed. This is then followed by simulations of inverters and ring oscillators to assess the results against simple logic circuits.

Novel Current-Mode All-Pass Filter with Minimum Component Count

Abstract: In this paper, two novel first order current- mode all-pass filters are proposed using a resistor and a grounded capacitor along with a mult i-output dual-X second-generation current conveyor (MO-DXCCII). There is no element matching restriction. Both the circuits exh ibit low input and high output impedance, which is a desirab le feature for current-mode circuits. The proposed circuits are simulated using SPICE simu lation program to confirm the theory.

A Compact SPICE Model of Unipolar Memristive Devices

Abstract: This paper introduces a compact SPICE model of unipolar memristive devices. The model is based on the unipolar memristive system equations with the assistance of two resistance switching velocity functions for controlling the SET and RESET processes, respectively. Our model is highly parameterized by providing various adjustable model parameters. We verify the functionality of our model by the HSPICE simulation with parameters abstracted from a real device and a previous model. As an example of model application, we successfully use the model to simulate the stateful logic operations of the memristive implication gate circuit. Compared with previous models, the proposed model is of good efficiency, accuracy, and usability.

Hardware-Software Subsystem for MOSFETs Characteristic Measurement and Parameter Extraction with Account for Radiation Effects

Abstract: Hardware-software subsystem designed for MOSFETs characteristic measurement and SPICE model parameter extraction taking into account radiation effects is presented. Parts of the system are described. The macromodel approach is used to account for radiation effects in MOSFET modeling. Particularities of the account for radiation effects in MOSFETs within the measurement and model parameter extraction procedures are emphasized. Application of the subsystem is illustrated on the example of radiation hardened 0.25 μm SOI MOSFET test structures.

Fast monte carlo statistical analysis using threshold voltage modeling

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations Circuit designers may capture design sensitivity to manufacture process changes more easily with simplified statistical models

Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators

Abstract: In this paper, we present a hybrid operational amplifier (opamp) frequency compensation topology to maximize a unity-gain bandwidth (UGBW) particularly for use in continuous-time delta-sigma modulators (CT ΔΣMs). Unlike well-known existing compensation topologies [1], the proposed compensation technique provides both a maximum UGBW and an adequate phase margin (PM) by appropriate non-dominant pole and zero positions. The proposed topology performance is validated by SPICE simulation using 28nm CMOS device models.

Simulation of CAN bus physical layer using SPICE

Abstract: This paper deals with a computational simulation of high speed CAN bus physical layer using SPICE. At the beginning, the general electric parameters of the physical layer are described - these parameters are in compliance with the international standard ISO 11898-2. The next part of the paper describes a SPICE library, which contains all basic electronic parts of physical layer, including CAN transceivers, transmission lines, common mode chokes and ESD protections. The model of ESD generator is also included in the library. In the paper are shown the most important results from the illustrative simulation and the results are compared with the results of the experimental measurement.

New Approach for Transient Radiation SPICE Model of CMOS Circuit

Abstract: Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

Spice seasoning and preparation method thereof

Abstract: The invention provides a spice seasoning and a preparation method thereof. The spice seasoning comprises the following raw materials in parts by weight: 6-10 parts of spice essential oil and/or oleoresin, 15-25 parts of edible salt powder, 5-10 parts of gourmet powder, 10-15 parts of white sugar powder and 40-55 parts of edible starch. The spice seasoning has the beneficial effects that according to the set formula and proportion, the spice seasoning prepared from spice essential oil and/or oleoresin enables active ingredients of the spice to be completely utilized, and the spice seasoning has rich flavor and pure mouth feel, is free of impurities such as plant fiber and the like, and is elegant in appearance and convenient to use; and meanwhile, the deep-processing technological content of the spice is promoted, and the types of the spice are enriched.