Showing papers on "Transistor published in 1997"

Electrosurgical generator and system for underwater operation

Abstract: A radio frequency generator for an electrosurgical system is provided, the system including an electrode assembly having two electrodes for use immersed in an electrically conductive fluid. The generator has control circuitry for rapidly reducing the delivered radio frequency output power by at least 50 % within at most a few cycles of the peak radio frequency output voltage reaching a predetermined threshold limit. In this way, tissue coagulation can be performed in, for example, saline without significant steam generation. The same peak voltage limitation technique is used in a tissue vaporisation or cutting mode to limit the size of the steam pocket at the electrodes and to avoid electrode burning. The generator has a push-pull output stage with a series-resonant output circuit, the output stage being driven by a radio frequency oscillator at a frequency which, in general, differs from the resonant frequency of the resonant output circuit. Power control is achieved by varying the ON-time of switching transistors forming the push-pull output pair and by altering the frequency spacing between the excitation frequency and the resonant frequency of the series-resonant output circuit. In an alternative embodiment, a bridge configuration using two push-pull pairs is used, yielding a further power control variable: the relative phase of the driving signals to the respective transistor pairs.

High-performance plastic transistors fabricated by printing techniques

Abstract: A printed field-effect transistor (FET) is reported, in which all the essential components are screen-printed for the first time. This transistor has a polyimide dielectric layer, a regioregular poly(3-alkythiophene) semiconducting layer, and two silver electrodes, all of which are printed on an ITO-coated plastic substrate.

A silicon single-electron transistor memory operating at room temperature

Abstract: A single-electron memory, in which a bit of information is stored by one electron, is demonstrated at room temperature. The memory is a floating gate metal-oxide-semiconductor transistor in silicon with a channel width (∼10 nanometers) smaller than the Debye screening length of a single electron and a nanoscale polysilicon dot (∼7 nanometers by 7 nanometers) as the floating gate embedded between the channel and the control gate. Storing one electron on the floating gate screens the entire channel from the potential on the control gate and leads to (i) a discrete shift in the threshold voltage, (ii) a staircase relation between the charging voltage and the shift, and (iii) a self-limiting charging process. The structure and fabrication of the memory should be compatible with future ultralarge-scale integrated circuits.

Measurement of piezoelectrically induced charge in GaN/AlGaN heterostructure field-effect transistors

Abstract: Electron concentration profiles have been obtained for AlxGa1−xN/GaN heterostructure field-effect transistor structures Analysis of the measured electron distributions demonstrates the influence of piezoelectric effects in coherently strained layers on III-V nitride heterostructure device characteristics Characterization of a nominally undoped Al015Ga085N/GaN transistor structure reveals the presence of a high sheet carrier density in the GaN channel which may be explained as a consequence of piezoelectrically induced charges present at the Al015Ga085N/GaN interface Measurements performed on an Al015Ga085N/GaN transistor structure with a buried Al015Ga085N isolation layer indicate a reduction in electron sheet concentration in the transistor channel and accumulation of carriers below the Al015Ga085N isolation layer, both of which are attributable to piezoelectric effects

A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

Abstract: Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high-speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the noise equations are coupled with scalable variants of the HICUM and SPICE-Gummel-Poon models and are employed in the design of tuned low noise amplifiers (LNA's) in the 1.9-, 2.4-,and 5.8-GHz bands.

Scanning Single-Electron Transistor Microscopy: Imaging Individual Charges

Abstract: A single-electron transistor scanning electrometer (SETSE)—a scanned probe microscope capable of mapping static electric fields and charges with 100-nanometer spatial resolution and a charge sensitivity of a small fraction of an electron—has been developed. The active sensing element of the SETSE, a single-electron transistor fabricated at the end of a sharp glass tip, is scanned in close proximity across the sample surface. Images of the surface electric fields of a GaAs/AlxGa1−xAs heterostructure sample show individual photo-ionized charge sites and fluctuations in the dopant and surface-charge distribution on a length scale of 100 nanometers. The SETSE has been used to image and measure depleted regions, local capacitance, band bending, and contact potentials at submicrometer length scales on the surface of this semiconductor sample.

A gate-level leakage power reduction method for ultra-low-power CMOS circuits

Abstract: In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing the power supply voltage. This requires that the transistor threshold voltages be reduced as well to maintain adequate performance and noise margins. However, this increases the subthreshold leakage current of p and n MOSFETs, which starts to offset the power savings obtained from power supply reduction. This problem will worsen in future generations of technology, as threshold voltages are reduced further. In order to overcome this, we propose a design technique that can be used during logic design in order to reduce the leakage current and power. We target designs where parts of the circuit are put in "standby" mode when not in use, which is becoming a common approach for low power design. The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated. We give an efficient algorithm for computing a good low leakage power state. We demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54% for some circuits.

Magnetic Tunneling Applied to Memory (Invited)

Abstract: Random access magnetoresistive memories have been designed using anisotropic magnetoresistive (AMR) material and more recently giant magnetoresistive (GMR) material. The thin films in these memories have low sheet resistivities (about 10 Ω/sq), resulting in cell resistances of 10 to 100 Ω at competitive areal densities. High sense currents of a mA or more are required to get signals on the order of a few mV. Spin dependent tunneling (SDT) devices are intrinsically high impedance, with typical equivalent resistance values of 104–109 Ω for a square micron area. SDT cells have the potential for signals on the order of 10 mV with lower sense currents, and hence, faster access times than GMR memory. A GMR pseudospin valve memory concept is presented for comparison with SDT memory. Three different design approaches are discussed for SDT memory: (1) high-density memory arrays similar to those in AMR and GMR memories, (2) a transistor per cell approach similar to semiconductor dynamic random access memory, and (3) embedded SDT devices in a flip–flop cell similar to semiconductor static random access memory. The conclusions are: (1) SDT memory is potentially higher speed than GMR memory, (2) SDT memory has no area advantage compared with dense GMR memory, and (3) risks with SDT memory include (a) processing ultrathin dielectric layers uniformly and reliably that are compatible with integrated circuits and (b) attaining sufficiently low impedance levels to get a satisfactory signal-to-noise ratio in a small area cell.

High-voltage double-implanted power MOSFET's in 6H-SiC

Abstract: We report on the first planar high-voltage MOSFET's in 6H-SiC. A double-implant MOS (DIMOS) process is used. The planar structure ameliorates the high-field stressing encountered by SiC UMOS transistors fabricated by other groups. Blocking mode operation of up to 760 V is demonstrated, which is nearly three times higher than previously reported operating voltages for SiC MOSFET's.

modern semiconductor device physics

Abstract: Bipolar Transistors (P Asbeck) Compound-Semiconductor Field-Effect Transistors (M Shur & T Fjeldly) MOSFETs and Related Devices (S Hillenius) Power Devices (B Baliga) Quantum-Effect and Hot-Electron Devices (S Luryi & A Zaslavsky) Active Microwave Diodes (H Eisele & G Haddad) High-Speed Photonic Devices (T Lee & S Chandrasekhar) Solar Cells (M Green) Appendices Index

Intrinsic MOSFET parameter fluctuations due to random dopant placement

Abstract: Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.

Transistor sizing issues and tool for multi-threshold CMOS technology

Abstract: Multi-threshold CMOS is an increasingly popular circuitapproach that enables high performance and low power operation.However, no methodologies have been developed to size the highV{t} sleep transistor in an intelligent manner that trades off area andperformance. In fact, many attempts at sizing the sleep transistorwithout close consideration of input vector patterns or internalstructures can lead to large overestimates or large underestimatesin sleep transistor sizing. This paper describes some of the issuesinvolved in sizing transistors for MTCMOS and also introduces avariable breakpoint switch level simulator that can rapidly calculatedelay in MTCMOS circuits as functions of design variablessuch as V{dd}, V{t}, and sleep transistor sizing.

Single-crystal Si films for thin-film transistor devices

Abstract: The fact that single-crystal Si would make an ideal material for thin-film transistor devices has long been recognized. Despite this awareness, a viable method by which such a material could be directly produced on a glass substrate has never been formulated. In this letter, it is shown experimentally that location-controlled single-crystal Si regions on a SiO2 surface can be obtained in a glass-substrate compatible manner, via excimer-laser-based sequential lateral solidification of thin Si films using a beamlet shape that self-selects and extends a single grain over an arbitrarily large area. This is accomplished by controlling the locations, shape, and extent of melting induced by the incident excimer-laser pulses, in such a manner as to induce interface-contour-affected sequential super-lateral growth of crystals, during which the tendency of grain boundaries to align approximately orthogonal to the solidifying interface is systematically exploited.

Method and apparatus for designing circuits for wave pipelining

Abstract: A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.

Room temperature operation of a quantum-dot flash memory

Abstract: A flash-memory device has been fabricated and demonstrated at room temperature by coupling a self-aligned, sub-50-nm quantum dot to the channel of a transistor on a silicon-on-insulator (SOI) substrate. Large threshold voltage shifts of up to 0.75 V are obtained for small erase/write voltages (13 V) at room temperature. At 90 K, evidence of single electron storage is observed. The small size of this device is attractive for achieving high packing densities, while the relatively large output current (100 nA-/spl mu/A's), low off-state current (10 pA), and simple fabrication, requiring only minor variations in standard processing, make it suitable for integration with current silicon memory and logic technology.

Single-electron floating-gate mos memory

Abstract: A Single Electron MOS Memory (SEMM), in which one bit of information is represented by storing only one electron, has been demonstrated at room temperature. The SEMM is a floating gate Metal-Oxide-Semiconductor (MOS) transistor in silicon with a channel width (about 10 nanometers) which is smaller than the Debye screening length of a single electron stored on the floating gate, and a nanoscale polysilicon dot (about 7 nanometers by 7 nanometers by 2 nanometers) as the floating gate which is positioned between the channel and the control gate. An electron stored on the floating gate can screen the entire channel from the potential on the control gate, and lead to: (i) a discrete shift in the threshold voltage; (ii) a staircase relation between the charging voltage and the shift; and (iii) a self-limiting charging process. The structure and fabrication of the SEMM is well adapted to the manufacture of ultra large-scale integrated circuits.

Quantum mechanical effects in the silicon quantum dot in a single-electron transistor

Abstract: The quantum mechanical effects in silicon single-electron transistors have been investigated. The devices have been fabricated in the form of point contact metal–oxide–semiconductor field-effect transistors with various channel widths using electron beam lithography and the anisotropic etching technique on silicon-on-insulator substrates. The device with an extremely narrow channel shows Coulomb blockade oscillations at room temperature. At low temperatures, negative differential conductances and fine structures are superposed on the device characteristics, which are attributed to the quantum mechanical effects in the silicon quantum dot in the channel. The energy spectrum of the dot is extracted from the experimental results.

Low voltage EEPROM/NVRAM transistors and making method

Abstract: A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells. With the feature of the vertical injection step, high injection efficiency can be achieved at much lower operating voltages, and program time is decreased, which has been a limiting factor in EEPROM applications. Operation at lower voltages improves reliability and overall process complexity. The feature of high injection efficiency at low drain voltage also makes multi-level storage easier and more controllable since the storage of electrons can be controlled by a single control gate voltage. This high efficiency, low voltage, step channel enables a single polysilicon EPROM transistor. Also, a double polysilicon EEPROM transistor with the vertical injection step near drain can achieve erase capability of polysilicon to polysilicon, something that could only be practically built with a triple polysilicon EEPROM cell, in prior art. This combination of a low voltage program and poly to poly erase in a double polysilicon split gate cell with the vertical injection step achieves the non-volatile RAM feature of write 0 (program) or 1 (erase) for a selected word line (control gate) at once. Fabrication methods for the vertical injection step channel near drain are also be described.

SPICE Models for Amorphous Silicon and Polysilicon Thin Film Transistors

Abstract: We describe physically based analytical models for n‐channel amorphous silicon thin film transistors and for n‐ and p‐channel polysilicon thin film transistors. The models cover all regimes of transistor operation: leakage, subthreshold, above‐threshold conduction, and the kink regime in polysilicon thin film transistors. The models contain a minimum number of parameters which are easily extracted and can be readily related to the structural and material properties of the thin film transistors. The models have been verified for a large number of devices to scale properly with device geometry.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

Abstract: Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance. To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Abstract: A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Pass gate circuit with body bias control

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

FET having a Si/SiGeC heterojunction channel

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Isolated gate driver for power switching device and method for carrying out same

Abstract: An isolated gate driver device for a power switching device having a plurality of transistors includes a primary circuit having a voltage source of a first voltage potential. The primary circuit constantly switches the voltage source to generate first and second load signals based on control signals received from a microcontroller. The first load signal is modulated at a first frequency for enabling the transistors, and the second load signal is modulated at a second frequency, different from the first frequency, for disabling the transistors. A plurality of high frequency transformers corresponding to each of the transistors is coupled to the primary circuit. The transformers have a primary side for receiving one of the first and second load signals and a secondary side for transforming the one of the first and second load signals into corresponding signals at a second voltage potential. A secondary circuit coupled between each of the transformers and each of the corresponding transistors provides a bias power supply to each of the transistors at the second voltage potential. The secondary circuit also enables and disables each of the transistors based on the first and second load signals.

Technology challenges for integration near and below 0.1 /spl mu/m

Abstract: Technology challenges for silicon integrated circuits with a design rule of 0.1 /spl mu/m and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 /spl mu/m currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 /spl mu/m which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 /spl mu/m technology. 0.1 /spl mu/m technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 /spl mu/m are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 /spl mu/m are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 /spl mu/m is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput.

Memory cell that includes a vertical transistor and a trench capacitor

Abstract: A memory cell for a dynamic random access memory includes a pass transistor and a storage capacitor. The transistor is a vertical transistor formed along an upper portion of a sidewall of a polysilicon-filled trench in a monocrystalline silicon body with the source and drain in the body and the source contact, gate and gate contact in the trench, with its gate dielectric being an oxide layer on the sidewall portion of the trench. The capacitor is a vertical capacitor formed along a deeper portion of the trench and has as its storage plate a lower polysilicon layer in the trench and as its reference plate a deep doped well in the body. The source contact and the storage plate are in electrical contact in the trench and the source contact and the gate contact are in the trench electrically isolated from one another.

Semiconductor device having ferroelectric capacitor structures

Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.

Frequency dependent signal transfer in neuron transistors

Abstract: Nerve cells are attached to open, metal-free gates of field-effect transistors submersed in electrolyte. The intracellular voltage is modulated by small ac signals from 0.1 Hz to 5000 Hz using a patch-clamp technique. The source-drain current is affected in amplitude and phase through a modulation of the extracellular voltage in the cleft between transistor and cell. The ac-signal transfer is evaluated on the basis of linear response theory. We use the model of a planar two-dimensional cable which consists of the core of an electrolyte sandwiched between the coats of a cell membrane and silicon dioxide of the transistor surface. Comparing experiment and model we obtain the resistances of core and coat, i.e., of the seal of cell and surface and of the attached membrane. The resistance of the membrane varies in different junctions. It may be lowered by two orders of magnitude as compared with the free membrane. This drop of the membrane resistance correlates with an enhancement of the seal resistance, i.e., with closer adhesion. The linear ac-transfer functions are used to compute the signal transfer of an action potential. The computed response is in good agreement with the observations of excited nerve cells on transistors.

Full-wave rectifier and method of operation for a recognition system

Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (VDD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).