Showing papers on "Voltage regulator published in 2017"
TL;DR: A nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS, equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified and lower THD can be obtained without HFM methods.
Abstract: Increasing demands for power supplies have contributed to the population of high-frequency ac (HFAC) power distribution system (PDS), and in order to increase the power capacity, multilevel inverters (MLIs) frequently serving as the high-frequency (HF) source-stage have obtained a prominent development. Existing MLIs commonly use more than one voltage source or a great number of power devices to enlarge the level numbers, and HF modulation (HFM) methods are usually adopted to decrease the total harmonic distortion (THD). All of these have increased the complexity and decreased the efficiency for the conversion from dc to HF ac. In this paper, a nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS. It makes full use of the conversion of series and parallel connections of one voltage source and two capacitors to realize nine output levels, thus lower THD can be obtained without HFM methods. The voltage stress on power devices is relatively relieved, which has broadened its range of applications as well. Moreover, the proposed nine-level inverter is equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified. The circuit structure, modulation method, capacitor calculation, loss analysis, and performance comparisons are presented in this paper, and all the superior performances of the proposed nine-level inverter are verified by simulation and experimental prototypes with rated output power of 200 W. The accordance of theoretical analysis, simulation, and experimental results confirms the feasibility of proposed nine-level inverter.
163 citations
TL;DR: A novel light load improvement mechanism is proposed by dynamically changing the bus voltage from 12 to 6 V during light load by which the system can achieve a more than 8% efficiency improvement.
Abstract: Efficient power delivery architecture is gaining more attention in the design of future generations of data centers in order to minimize the ever increasing trend of power consumption Silicon-based power delivery architectures and designs have already reached a level of maturity in terms of efficiency and density Recent studies indicate that 48-V voltage regulator modules (VRMs), instead of 12-V VRMs, are deemed a more efficient and cost effective architecture In this paper a Gallium Nitride (GaN) based design of a two-stage solution is proposed The first stage is a 48 V/12 V-250 W LLC converter with a matrix transformer design operating at 16 MHz with a peak efficiency of 973% and a power density of 870 W/in3 The second stage is a 12/18 V multiphase buck converter which can be either a conventional silicon-based or a GaN-based design with a higher operating frequency and power density Furthermore, in this proposed two-stage architecture, a novel light load improvement mechanism is proposed by dynamically changing the bus voltage from 12 to 6 V during light load by which the system can achieve a more than 8% efficiency improvement
143 citations
TL;DR: A subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors, which achieves a line sensitivity of 0.31%/V and a power supply rejection of −41 dB while consuming 35 pW from 1.4 V at room temperature.
Abstract: This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low-power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking one or more PMOS transistors. The temperature coefficient of the reference voltage is compensated by setting the size ratio of the native NMOS and stacked pMOS transistors to cancel temperature dependence of transistor threshold voltage and thermal voltage. Also, the transistor size is determined considering the trade-off between diode current between n-well and p-sub and process variation. Prototype chips are fabricated in a 0.18- $\mu \text{m}$ CMOS process. Measurement results from three wafers show $3\sigma $ inaccuracy of ±1.0% from 0 °C to 100 °C after a single room-temperature trim. The proposed voltage reference achieves a line sensitivity of 0.31%/V and a power supply rejection of −41 dB while consuming 35 pW from 1.4 V at room temperature.
142 citations
TL;DR: In this paper, the authors analyzed the stability of digitally voltage-controlled voltage-source inverters (VSIs) with the linear voltage regulators and proposed an enhanced voltage control approach with a widened stability region, and a step-by-step design method of the proposed controller was developed based on the root contours in the discrete z-domain.
Abstract: This paper analyzes the stability of digitally voltage-controlled voltage-source inverters (VSIs) with the linear voltage regulators. It is revealed that the phase lags, caused by using the resonant controller and the time delay of a digital control system, can stabilize the single-loop voltage control without damping of the LC -filter resonance. The stability region for the digital single-loop resonant voltage control is then identified, considering the effects of different discretization methods for the resonant controller. An enhanced voltage control approach with a widened stability region is subsequently proposed, and a step-by-step design method of the proposed controller is developed based on the root contours in the discrete z -domain. Simulations and experimental tests of a 400-Hz VSI system validate the stability analysis and the performance of the proposed control approach.
123 citations
TL;DR: In this article, the authors provide a comprehensive review on the DVR topologies, control strategies and applications, and some comparative conclusions are also provided for the researchers and engineers, who want to do investigations on DVRs.
123 citations
TL;DR: In this paper, a two-phase interleaved LLC (iLLC) resonant converter with hybrid rectifier is proposed for wide output voltage range applications, where the primary sides of the two LLC converters are in parallel, and the connection of the secondary windings can be regulated by the hybrid rectifiers according to the output voltage.
Abstract: A family of two-phase interleaved LLC (iLLC) resonant converter with hybrid rectifier is proposed for wide output voltage range applications. The primary sides of the two LLC converters are in parallel, and the connection of the secondary windings in the two LLC converters can be regulated by the hybrid rectifier according to the output voltage. Variable frequency control is employed to regulate the output voltage and the secondary windings are in series when the output voltage is high. Fixed-frequency phase-shift control is adopted to regulate the configuration of the secondary windings as well as the output voltage when the output voltage is low. The output voltage range is extended by adaptively changing the configuration of the hybrid rectifier, which results in reduced switching frequency range, circulating current, and conduction losses of the LLC resonant tank. Zero voltage switching and zero current switching are achieved for all the active switches and diodes, respectively, within the entire operation range. The operation principles are analyzed and a 3.5 kW prototype with 400 V input voltage and 150–500 V output voltage is built and tested to evaluate the feasibility of the proposed method.
122 citations
TL;DR: It is shown that the proposed Controller for automatic voltage regulator (AVR) provides the better time response characteristics than the other existing techniques.
102 citations
TL;DR: A case study dealing with long-term voltage instability in systems hosting active distribution networks (DN) anticipates future situations with high penetration of dispersed generation (DG), where the latter are used to keep distribution voltages within desired limits, in complement to load tap changers.
Abstract: A case study dealing with long-term voltage instability in systems hosting active distribution networks (DN) is reported in this paper. It anticipates future situations with high penetration of dispersed generation (DG), where the latter are used to keep distribution voltages within desired limits, in complement to load tap changers. The interactions between transmission and active DN are investigated on a 3108-bus test system. It involves transmission grid, large generators, and 40 DN, each with DG steered by a controller inspired by model predictive control. The reported simulations show the impact of distribution network voltage restoration, as well as the benefit of load voltage reduction actuated by the dispersed generators.
95 citations
TL;DR: In this paper, a non-isolated converter topology with very high step-down conversion ratio and high efficiency for high current low voltage point-of-load voltage regulator modules is introduced.
Abstract: This paper introduces a new nonisolated converter topology with very high step-down conversion ratio and high efficiency for high current low voltage point-of-load voltage regulator modules. Compared to a conventional two-phase buck converter, the new converter triples the effective duty-ratio and lowers the voltage stress of the transistors, significantly reducing the overall volume of the converter while maintaining high efficiency. The new converter is capable of delivering high current to the output by two interleaved phases and further features an inherent current sharing to balance the load between the phases. The use of lower voltage stress transistors allows operation at high switching frequencies that translates into fast dynamic response to load perturbations. The operation of the topology is verified on a 30 W, 48 V-to-1 V prototype, demonstrating peak efficiency of 91.5% and above 88% for most of the load range.
91 citations
TL;DR: In this paper, the authors investigated the effectiveness and general performance of different reactive and active power control concepts, including photovoltaic generators and power curtailment, in low voltage networks.
Abstract: In some rural and sub-urban areas, the hosting capacity (HC) of low voltage networks is restricted by voltage limits. With local voltage control, photovoltaic generators can mitigate the voltage rise partly and, therefore, increase the HC. This paper investigates the effectiveness and general performance of different reactive and active power control concepts. It presents the findings of an extensive simulation-based investigation into the effectiveness of voltage rise mitigation, additional reactive power flows, network losses, and power curtailment. The two most common implementations of reactive power control have a similar effectiveness. The voltage rise can be compensated for by up to 25% and more than 60% for typical cable and overhead (OH) feeders, respectively. By additionally using active power curtailment of up to 3% of the annual yield, the HC can be increased by about 50% and 90% for the considered cable and OH feeder, respectively (purely rural feeders).
88 citations
TL;DR: In this paper, the combined model of automatic load frequency control (ALFC) and automatic voltage regulator (AVR) of a multisource multi-area system for control of voltage, frequency and tie-line power is presented.
Abstract: This study presents the combined model of automatic load frequency control (ALFC) and automatic voltage regulator (AVR) of a multisource multi-area system for control of voltage, frequency and tie-line power. Each area comprises of a solar thermal, thermal and diesel plant. A more realistic system is studied by considering generation rate constraint and governor dead band (GDB) for the thermal plant. Integral (I)-double derivative (DD) controller with derivative (D) filter (IDDF) is proposed for the combined ALFC and AVR model by considering 1% step load perturbation in area1. The controller parameters are optimised using lightning search algorithm (LSA). The performance of proposed controller is compared with other conventional controllers such as proportional-I (PI), I-D and PI-D. The analysis reveals that the proposed controller outperforms the others in terms of settling time and peak deviations. The comparative performance of various performance indices shows that integral squared error is better than others. Analysis of the effect of GDB with IDDF controller and LSA indicates that the presence of GDB leads to more oscillations in the system dynamics. The sensitivity analysis against the change in magnitude and position of disturbance derived the robustness of the IDDF controller parameters obtained at nominal condition.
TL;DR: Simulation and experimental studies show that CMV injection significantly reduces the capacitor voltage ripple and the CC in legs and the proposed approach also improves output voltage and current waveform quality.
Abstract: Submodule (SM) capacitor voltage ripple is one of the major concerns in modular multilevel converters (MMCs). Capacitor voltage ripple leads to the double-frequency circulating current (CC) in legs, thereby resulting in a cascading effect of increased peak value of the arm current, semiconductor device stress, and power losses in MMCs. In this study, a model predictive control (MPC) with common-mode voltage (CMV) injection is proposed to minimize capacitor voltage ripple and the magnitude of CC. A discrete-time mathematical model of the MMC with CMV is presented to predict the future behavior of the control variables. The injection of CMV guarantees arm voltage balancing without CC control and long-term stability of MMC without large capacitors. The dynamic and steady-state performances of MPC with CMV injection are verified on an MMC with three-level flying capacitor SMs. A performance comparison between the proposed approach and the conventional MPC is also presented. Simulation and experimental studies show that CMV injection significantly reduces the capacitor voltage ripple and the CC in legs. The proposed approach also improves output voltage and current waveform quality.
TL;DR: A distributed control method is proposed to simultaneously optimize the power sharing among sources of islanded dc microgrids, while regulating the distribution bus voltage using a voltage regulator and optimizer to establish the generation-consumption equality constraint and matches the incremental costs.
Abstract: A distributed control method is proposed to simultaneously optimize the power sharing among sources of islanded dc microgrids, while regulating the distribution bus voltage. During the optimization process, an economic dispatch problem is solved to minimize the total generation cost by setting the output powers of the dispatchable sources. To this end, the voltage set points of individual dc–dc converters are adjusted using a voltage regulator and an optimizer, which regulates the average voltage of the sources to establish the generation–consumption equality constraint and matches the incremental costs, respectively. Afterward, the proposed optimizer is modified to exclude the sources from the incremental cost consensus protocol upon reaching their generation limits, enforcing inequality constraints. This coregulation and cooptimization paradigm is developed in a fully distributed fashion. The dynamical model of the proposed controller is established. The steady-state analysis verifies the fulfillment of the control objectives, i.e., voltage regulation and cost minimization. Experimental results verify the controller performance and validate its resiliency against cyber and physical faults.
TL;DR: In this article, the authors examined the use of superconducting magnetic and battery hybrid energy storage to compensate grid voltage fluctuations and showed that the SMES/battery hybrid dynamic voltage restorer can support both short-term high-power voltage sags and long-term undervoltages.
Abstract: This study examines the use of superconducting magnetic and battery hybrid energy storage to compensate grid voltage fluctuations. The superconducting magnetic energy storage system (SMES) has been emulated by a high-current inductor to investigate a system employing both SMES and battery energy storage experimentally. The design of the laboratory prototype is described in detail, which consists of a series-connected three phase voltage source inverter used to regulate ac voltage, and two bidirectional dc/dc converters used to control energy storage system charge and discharge. “DC bus level signaling” and “voltage droop control” have been used to automatically control power from the magnetic energy storage system during short-duration, high-power voltage sags, while the battery is used to provide power during longer term, low-power undervoltages. Energy storage system hybridization is shown to be advantageous by reducing battery peak power demand compared with a battery-only system, and by improving long-term voltage support capability compared with an SMES-only system. Consequently, the SMES/battery hybrid dynamic voltage restorer can support both short-term high-power voltage sags and long-term undervoltages with significantly reduced superconducting material cost compared with an SMES-based system.
TL;DR: In this article, a two-stage circuit topology is proposed, wherein the first stage is a boost converter, which serves for maximum power point tracking, and the second stage is grid tied voltage source converter (VSC), which not only feeds extracted solar photovoltaic (PV) energy into the three phase distribution system but also serves for harmonics mitigation, reactive power compensation, and grid current balancing.
Abstract: This paper presents a grid supported solar energy conversion system with an adjustable dc link voltage for common point of interconnection (CP) voltage variations. A two-stage circuit topology is proposed, wherein the first stage is a boost converter, which serves for maximum power point tracking, and the second stage is a grid tied voltage source converter (VSC), which not only feeds extracted solar photovoltaic (PV) energy into the three-phase distribution system but also serves for harmonics mitigation, reactive power compensation, and grid current balancing. An interweaved double-frequency second-order generalized integrator-based control algorithm is proposed for control of this multifunctional VSC, which possesses the feature of good steady-state performance along with fast dynamic response even under sudden load changes at CPI. Moreover, a feed-forward term for the solar PV contribution is used to enhance the dynamic response for climatic changes and CPI voltage variation. An adjustable dc link voltage structure is used to accommodate CPI voltage variation, which helps in reduction of losses in the power circuit. To implement adjustable dc link voltage structure, the reference dc link voltage is adjusted with variation in CPI voltage in real time. A proportional–integral controller is used to regulate dc link voltage to set reference value. A wide range of experimental results are shown to demonstrate the features of the proposed system. The total harmonic distortion of grid current has been found well under IEEE-519 standard even under nonlinear loads at CPI.
TL;DR: A new fractional order PID controller designing method is proposed AVR system based on Bodes reference model and extensive simulations and comparisons show that the designed FOPID controller has more excellent performance.
Abstract: Automatic voltage regulator (AVR) system is an important equipment in power system for maintaining the terminal voltage of the generator at a specific level. Recently, fractional order PID controller has been designed for AVR system. However, many fractional order PID controller designing methods need to calculate various performance indices in time domain and frequency domain in the process of parameter tuning, which is a tedious and complex process and satisfactory performance can not be obtained. In this paper, a new fractional order PID controller designing method is proposed AVR system based on Bodes reference model. The optimal parameters of FOPID controller is obtained through minimizing the integrated absolute error (IAE) between the output of the Bodes ideal reference model and that of the plant. Particle swarm optimization (PSO) is responsible to search the solution of the IAE criterion, i.e., the parameters of FOPID controller. Extensive simulations and comparisons show that the designed FOPID controller has more excellent performance. Meanwhile, PSO algorithm is effective for searching the optimal FOPID controller parameters.
TL;DR: In this article, a master-slave output current differential (OCD) control scheme was proposed to enable low-voltage converters to be used for highvoltage specifications.
Abstract: This paper proposes an output current-differential (OCD) control scheme that has a master–slave structure. It can be applied in dc/dc converters to connect the input in series and the output in parallel. All of the control and sample circuits in the proposed control scheme are on the output side, which means that there is no further isolation in the control loops. The proposed control scheme, consisting of one output voltage regulator loop and individual load-current-sharing loops, will enable low-voltage converters to be used for high-voltage specifications. The master module regulates the output voltage through a common output voltage loop and provides current references to slave modules. The individual current-sharing loops residing in the slave modules regulate the current in each module equally. According to the power balance, input-voltage sharing is realized simultaneously. To prevent a situation in which system failure is caused by master module failure, a fault-tolerant automatic master–slave output current-differential (FOCD) control scheme is developed. The performance of the OCD and FOCD control schemes is validated on a 450-W prototype input-series–output-parallel system comprising three forward converters.
TL;DR: In this article, a single-stage PFC rectifier with two active switches, one inductor and one small power-buffering capacitor is proposed, which can achieve high power factor, wide output voltage range, and power decoupling function without using electrolytic capacitor.
Abstract: Conventional single-phase power-factor-correction (PFC) rectifiers with active power decoupling capability typically require more than three active switches in their circuits. By exploring the concept of power-buffer cell, a new single-stage PFC rectifier with two active switches, one inductor and one small power-buffering capacitor is reported in this paper. The proposed converter can achieve high-power factor, wide output voltage range, and power decoupling function without using electrolytic capacitor. Additionally, an automatic power decoupling control scheme that is simple and easy to implement is proposed in this paper. The operating principle, control method, and design considerations of the proposed rectifier are also provided. A 100-W prototype with ac input voltage of 110 Vrms and a regulated dc output voltage ranging from 30 to 100 V has been successfully designed and practically tested. The experimental results show that with only a 15 μ F power-buffering film capacitor, the proposed converter can achieve an input power factor of over 0.98, peak efficiency of 93.9%, and output voltage ripple of less than 3%, at 100-W output power.
01 Feb 2017
TL;DR: Improved PSCA resistance is demonstrated offered by an on-die all-digital high-frequency IVR in 130nm CMOS for a standard (unprotected) 128b Advanced Encryption Standard (AES) core designed in static CMOS logic.
Abstract: Power side-channel attacks (PSCA), e.g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve data-independent supply current patterns via implementation of crypto engines using non-conventional logic (complemented [1] or charge recovery [2]) and local switched-capacitor-based supply current equalization [3] have been demonstrated. The feasibility of using bandwidth-limited integrated low dropout regulators, multi-phase switched-capacitor VRs with phase-randomization and integrated inductive voltage regulators (IVR) to enhance PSCA resistance have been explored before via simulation studies [4]. In this paper, we demonstrate improved PSCA resistance offered by an on-die all-digital high-frequency IVR in 130nm CMOS [5] for a standard (unprotected) 128b Advanced Encryption Standard (AES) core designed in static CMOS logic. The IVR features a configurable digital proportional-integral-derivative (PID) controller, a digital discontinuous conduction mode (DCM) controller, and a loop randomization (LR) block, all of which are utilized to enhance PSCA resistance with minimal power/performance/area overheads, while maintaining adequate local voltage regulation and transient performance.
TL;DR: In this paper, a load current injection based improved load flow (LF) technique for modern distribution system is derived by promulgating the concept of conventional backward forward sweep technique, which uses a single load current to bus voltage (LCBV) matrix to perform both the backward and forward sweeps of power flow calculation in a single step.
TL;DR: In this article, a new approach is presented to solve the EVCC problem considering Volt-VAr control, energy storage device (ESD) operation and dispatchable distributed generation (DG) available in three-phase unbalanced electrical distribution networks (EDNs).
Abstract: In this paper, a new approach is presented to solve the electric vehicle charging coordination (EVCC) problem considering Volt-VAr control, energy storage device (ESD) operation and dispatchable distributed generation (DG) available in three-phase unbalanced electrical distribution networks (EDNs). Dynamic scheduling for the EVCC is proposed through a step-by-step methodology, which solves a mixed integer linear programming (MILP) problem for the whole time period. The objective is to minimize the total cost of energy purchased from the substation and DG units, the cost of energy curtailment on electric vehicles, the cost of energy injected from the ESDs, and the cost of energy curtailment on the ESDs. The Volt-VAr control considers the management of on-load tap changers, voltage regulators, and switchable capacitors installed along the grid. Furthermore, the formulation takes into account the voltage dependence of the loads, while the steady-state operation of the unbalanced distribution systems is modeled using linear constraints. The proposed model was tested in a 178-node three-phase unbalanced EDN considering a one-day time period.
TL;DR: In this article, an on-chip switched capacitor voltage regulator for granular power delivery with per-core regulation for microprocessor power delivery has been proposed, which has the potential to significantly improve the energy efficiency of future data centers.
Abstract: Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular power delivery with per-core regulation given a high efficiency, high power density, fast response time, and high output power converter design. This paper details the implementation of an on-chip switched capacitor voltage regulator in a $32\,\mathrm{n}\mathrm{m}$ SOI CMOS technology with deep trench capacitors. A novel feedforward control for reconfigurable switched capacitor converters is presented. The feedforward control reduces the output voltage droop following a transient load step. This leads to a reduced minimum microprocessor supply voltage, thereby reducing the overall power consumption of the microprocessor. The implemented on-chip switched capacitor voltage regulator provides a $0.7-1.1$ V output voltage from $1.8$ V input. It achieves a $85.1\%$ maximum efficiency at $3.2\,\mathrm{W}\mathrm{/}\mathrm{m}\mathrm{m}^2$ power density, a subnanosecond response time with improved minimum supply voltage capability, and a maximum output power of $10\,\mathrm{W}$ . For an output voltage of $850\,\mathrm{m}\mathrm{V}$ , the feedforward control reduces the required voltage overhead by $60\,\mathrm{m}\mathrm{V}$ for a transient load step from $10\%$ to $100\%$ of the nominal load. This can reduce the overall power consumption of the microprocessor by $7\%$ .
TL;DR: In this article, a parallel-connected diode-clamped M2C (DCM2C) was proposed, in which each arm consists of two parallel connected clusters, and an equal current distribution was achieved between the two clusters.
Abstract: The modular multilevel converter (MMC or M2C) is an emerging attractive multilevel topology for medium-voltage high-power applications. The capacitor voltage balancing control and the improvement of output current rating are two challenging issues of MMC. This paper proposed a new parallel-connected diode-clamped M2C (DCM2C), in which each arm consists of two parallel-connected clusters. In this topology, the capacitor voltages can be balanced automatically without any balancing control algorithms. Theoretically, no voltage sensors are needed to measure the capacitor voltages theoretically. Thus, the control of the converter can be simplified greatly. With a simple current-sharing control, an equal current distribution can be achieved between the two clusters. Furthermore, an extended parallel-DCM2C is proposed for larger current applications, and the corresponding current-sharing control method is developed. Experimental results validated the voltage self-balancing capability of parallel-DCM2C and the effectiveness of the proposed current-sharing control.
TL;DR: In this paper, the effects of flexible AC Transmission System (FACTS) devices in load flow problem by HELM technique is evaluated using the white germ solution along with recursive formula and controlling FACTS devices operation bounds.
Abstract: Development of appropriate load flow model of Flexible AC Transmission System (FACTS) devices is an important issue for proper planning, control, and protection of power system. Holomorphic Embedding Load-Flow Method (HELM) is a novel technique for solving load flow nonlinear equations which overcomes the numerical problems faced by traditional iterative techniques. In order to evaluate the effects of FACTS devices in load flow problem by HELM technique, it is necessary to develop HELM modeling of these devices. This paper presents HELM modeling of Thyristor-based FACTS controllers, i.e., Static Var Compensator (SVC), Thyristor Controlled Switched Capacitor (TCSC), Thyristor Controlled Voltage Regulator (TCVR), and Thyristor Controlled Phase Angle Regulator (TCPAR). In this modeling, white germ solution is investigated along with recursive formula and controlling FACTS devices operation bounds.
TL;DR: In this paper, a new method for measuring capacitor voltages in multilevel flying capacitor (FC) converters that requires only one voltage sensor per phase leg is proposed, which is subsequently used to balance the capacitor voltage using only the measured ac voltage.
Abstract: This paper proposes a new method for measuring capacitor voltages in multilevel flying capacitor (FC) converters that requires only one voltage sensor per phase leg. Multiple dc voltage sensors traditionally used to measure the capacitor voltages are replaced with a single voltage sensor at the ac side of the phase leg. The proposed method is subsequently used to balance the capacitor voltages using only the measured ac voltage. The operation of the proposed measurement and balancing method is independent of the number of the converter levels. Experimental results presented for a five-level FC converter verify effective operation of the proposed method.
TL;DR: The focus of the paper is to scale the off-chip output capacitor of an LDO conventionally used to compensate fast load current change to shrink the output capacitor size to shorten control latency.
Abstract: This paper presents a fully integrated digital low-dropout (LDO) voltage regulator based on event-driven control architecture. The focus of the paper is to scale the off-chip output capacitor of an LDO conventionally used to compensate fast load current change. To shrink the output capacitor size, it is paramount to shorten control latency. This can be done by employing a high-speed error amplifier in analog LDO designs and by using fast clock in digital synchronous LDO designs. However, those approaches become less suitable for sub-1-V supply voltage due to the headroom problem of analog circuits and/or increase power dissipation due to the high-frequency clock. In this paper, we tackle the tradeoff between power consumption and control latency by introducing an event-driven approach. Our event-driven approach enables to perform regulation tasks only when the output voltage deviates significantly from a set point, simultaneously achieving short latency and low-power dissipation. We prototyped an event-driven digital LDO that supports 400- $\mu \text{A}$ load current at 0.5-V input and 0.45-V output voltage. The measurements show 40-mV droop voltage and 96.3% peak current efficiency with an on-chip integrated 0.4-nF output capacitor.
TL;DR: Dual time-scale coordination for the Volt-VAR control scheme, corresponding to slow and fast control, is proposed and shown to be effective with respect to all possible scenarios in the uncertainty set, with little compromise in terms of network losses.
Abstract: In distribution networks, there are slow controlling devices and fast controlling devices for Volt-VAr regulation. These slow controlling devices, such as capacitors or voltage regulators, cannot be operated frequently and should be scheduled tens of minutes ahead (hereafter named as slow control). Since of the uncertainties in predicting the load and distributed generation, the voltage violations cannot be eliminated by fast controlling devices with improper schedule of the slow controlling devices. In this paper we propose dual time-scale coordination for the Volt-VAr control scheme, corresponding to slow and fast control. Slow control guarantees that subsequent fast controls can maintain the system's voltage security if the uncertain parameters vary within predefined limits. A column-and-constraint generation algorithm was used to solve the robust convexified model. A conventional deterministic optimization model can be used to determine the fast control mechanism. The simulation results show that solving the deterministic model is not always feasible and voltage violation may occur. The robust model was shown to be effective with respect to all possible scenarios in the uncertainty set, with little compromise in terms of network losses.
TL;DR: In this article, the authors examined and analyzed the control interactions among multiple Volt/VAr support DG units and voltage regulating devices such as tap changers and capacitor banks for effective voltage control in active distribution systems.
Abstract: Voltage regulation by means of coordinated voltage control is one of the challenging aspects in an active distribution system operation. Integration of distributed generation (DG), which can also be operated in Volt/VAr control mode, may introduce adverse effects including control interactions, operational conflicts, steady-state voltage variations, and oscillations. Therefore, examining and analyzing the phenomenon (both steady state and dynamic) of the control interactions among multiple Volt/VAr support DG units and voltage regulating devices such as tap changers and capacitor banks would be essential for effective voltage control in active distribution systems. In this paper, the interactions among DG units and voltage regulating devices are identified using their simultaneous and nonsimultaneous responses through time-domain simulations. For this task, an analytical technique is proposed and small signal modeling studies have been conducted. The proposed methodology could be beneficial to distribution network planners and operators to ensure seamless network operation from voltage control perspective with increasing penetration of DG units.
TL;DR: In this article, a discrete-time domain modeling of an LC plant with consideration of delay and sample-and-hold effects on the state feedback cross-coupling decoupling is derived.
Abstract: The decoupling of the capacitor voltage and inductor current has been shown to improve significantly the dynamic performance of voltage source inverters in standalone applications. However, the computation and pulse width modulation delays still limit the achievable bandwidth. In this paper, a discrete-time domain modeling of an LC plant with consideration of delay and sample-and-hold effects on the state feedback cross-coupling decoupling is derived. From this plant formulation, current controllers with wide bandwidth and good relative stability properties are developed. Two controllers based on lead compensation and Smith predictor design, respectively, are obtained. Subsequently, the voltage regulator is also designed for a wide bandwidth, which permits the inclusion of resonant filters for the steady-state mitigation of odd harmonics at nonlinear unbalance load terminals. Discrete-time domain implementation issues of an antiwind up scheme are discussed as well, highlighting the limitations of some discretization methods. Extensive experimental results, including a short-circuit test, verify the theoretical analysis.
TL;DR: A new voltage regulation control algorithm is designed for the buck-type dc-dc converter system in the presence of unknown input voltage and load variations that has a faster regulation performance and stronger performance on load-variation rejection.
Abstract: A new voltage regulation control algorithm is designed for the buck-type dc-dc converter system in the presence of unknown input voltage and load variations. To enhance the voltage regulation time by using the finite-time control theory, a new fast voltage regulation control algorithm is designed that can guarantee that the output voltage converges to the reference voltage in a finite time. To address the unknown input voltage and load variations, two finite-time convergent observers are designed to estimate the unknown parameters in a finite time. Finally, an adaptive finite-time control algorithm is developed. Compared with the PI control algorithm, experimental results show that the proposed algorithm has a faster regulation performance and stronger performance on load-variation rejection.