Journal ArticleDOI
A Compact Model for Double-Gate Heterojunction Tunnel FETs
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TLDR
In this paper, a compact model for generic heterojunction tunnel FETs (H-TFETs) is developed to simulate H-FTET formed by different source/body material systems.Abstract:
A compact model for generic heterojunction tunnel FETs (H-TFET) is developed to simulate H-TFET formed by different source/body material systems. The model is based on the device electrostatic potentials obtained from the solution of Poisson’s equation. After deriving the potential profile, the tunneling distance from the source to the channel is calculated by matching the boundary conditions between the two materials. The drain current, terminal charges, and capacitance are derived based on the electrostatics dictated by the tunneling distance. To improve the accuracy for lightly doped source H-TFET in p-type devices, the effect of source depletion is also included. The model has been implemented in a circuit simulator without convergence program. It has also been extensively verified by TCAD simulations and published data to show its validity.read more
Citations
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Journal ArticleDOI
2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure
Sanjay Kumar,Kunal Singh,Sweta Chander,Ekta Goel,Prince Kumar Singh,Kamalaksha Baral,Balraj Singh,Satyabrata Jit +7 more
TL;DR: In this paper, a continuous 2D analytical drain current model of double-gate (DG) heterojunction tunnel field effect transistors (HJTFETs) with a SiO2/HfO2 stacked gate-oxide structures is presented.
Journal ArticleDOI
An Accurate Analytical Current Model of Double-gate Heterojunction Tunneling FET
TL;DR: In this article, a continuous accurate analytical drain current model considering the effect of the inversion charge is presented for the double-gate heterojunction tunneling FET, which is calculated analytically in terms of the integration with respect to the generation rate using a tangent line approximation method.
Journal ArticleDOI
An Analytical Model of Gate-All-Around Heterojunction Tunneling FET
TL;DR: In this paper, a compact analytical drain current model considering the inversion layer and source depletion is developed for the gate-all-around (GAA) heterojunction tunneling FET (H-TFET) with staggered-gap alignment.
Journal ArticleDOI
An Analytical Drain Current Model for the Cylindrical Channel Gate-All-Around Heterojunction Tunnel FETs
TL;DR: In this article, the authors present analytical models which are valid in all regions of operation and can accurately predict the potential profile and the output, as well as the transfer characteristics of the gate-all-around heterojunction tunnel field effect transistors.
Journal ArticleDOI
ZnO/Si and ZnO/Ge bilayer tunneling field effect transistors: Experimental characterization of electrical properties
TL;DR: In this article, the electrical properties of bilayer TFETs with a heterotunneling junction composed of an oxide-semiconductor source and a group-IV semiconductor channel were investigated.
References
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Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
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Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Scaling the Si MOSFET: from bulk to SOI to bulk
R.-H. Yan,Abbas Ourmazd,K.F. Lee +2 more
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.