scispace - formally typeset

Proceedings ArticleDOI

Electrical property modelling of photodiode type CMOS active pixel sensor (APS)

S.U. Ay1
01 Jan 2005-pp 371-375

AbstractIn this research, few electrical characteristics of photodiode (PD) type CMOS active pixel sensor (APS) pixel were modeled. BSIM3v3 threshold voltage equation was simplified for hand calculation with better than 2% peak-to-peak error for full back-gate bias and supply voltages for CMOS process technologies that has minimum feature sizes between 0.18/spl mu/m and 2.0/spl mu/m. Two fitting function coefficients (FFC) were included in the BSIM threshold model equations for simplification of the equation. FFCs were extracted by using circuit simulation for given process. Using the simplified threshold equation, electrical characteristics of 3T CMOS PD-APS pixel were modeled. Models include; photodiode reset level, pixel amplifier signal range, and pixel reset level boosting factor. Models were evaluated by using wide variety of available CMOS process technologies and compared with the simulation results. Pixel reset level and signal range model equations produce better than 6% and 12% peak-to-peak accuracy with simple hand calculation, respectively. Models were also confirmed with a designed photodiode-type CMOS APS pixel. A CMOS photodiode type APS imager fabricated in a 0.5/spl mu/m, 2P3M, 5Volt CMOS process with 15/spl mu/m square pixel size was used for comparison.

Topics: CMOS sensor (63%), Photodiode (55%), CMOS (55%), BSIM (51%), Pixel (51%)

...read more

Content maybe subject to copyright    Report

Citations
More filters

Journal ArticleDOI
Suat U. Ay1
TL;DR: A CMOS image sensor capable of imaging and energy harvesting on same focal plane is presented for retinal prosthesis and its efficiency was measured at different light levels.
Abstract: A CMOS image sensor capable of imaging and energy harvesting on same focal plane is presented for retinal prosthesis. The energy harvesting and imaging (EHI) active pixel sensor (APS) imager was designed, fabricated, and tested in a standard 0.5 μm CMOS process. It has 54 × 50 array of 21 × 21 μm2 EHI pixels, 10-bit supply boosted (SB) SAR ADC, and charge pump circuits consuming only 14.25 μW from 1.2 V and running at 7.4 frames per second. The supply boosting technique (SBT) is used in an analog signal chain of the EHI imager. Harvested solar energy on focal plane is stored on an off-chip capacitor with the help of a charge pump circuit with better than 70% efficiency. Energy harvesting efficiency of the EHI pixel was measured at different light levels. It was 9.4% while producing 0.41 V open circuit voltage. The EHI imager delivers 3.35 μW of power was delivered to a resistive load at maximum power point operation. The measured pixel array figure of merit (FoM) was 1.32 pW/frame/pixel while imager figure of merit (iFoM) including whole chip power consumption was 696 fJ/pixel/code for the EHI imager.

39 citations


Cites background from "Electrical property modelling of ph..."

  • ...Signal dependent backgate bias voltage results in the threshold voltage of the pixel transistors (M1-M3) to increase [20]....

    [...]


Journal ArticleDOI
Suat U. Ay1
TL;DR: It was shown that the proposed boosted readout does not increase the number of transistors in the 3T CMOS APS pixels nor degrade the image quality, and provides additional 31% dynamic range improvement on top of the seven times (7×) expansion attained by boosting the pixel reset signal.
Abstract: A new pixel readout technique is proposed for three-transistor (3T) CMOS active pixel sensor (APS) pixels. It utilizes the supply-boosting technique (SBT) in order to reduce power consumption and allow ultra low-voltage operation. The pixel supply voltage as well as the pixel reset and select signals were boosted to achieve wider and extended linear operating ranges. A CMOS image sensor containing a 54 × 50 array of 3T CMOS APS pixels was fabricated in a standard 2P3M 5-V 0.5- μm CMOS process to confirm the effectiveness of each boosting operation. Theory, simulation, and measurement results are presented. The boosting pixel supply voltage during pixel readout provides additional 31% dynamic range improvement on top of the seven times (7×) expansion attained by boosting the pixel reset signal. It was shown that the proposed boosted readout does not increase the number of transistors in the 3T CMOS APS pixels nor degrade the image quality.

9 citations


Proceedings ArticleDOI
Suat U. Ay1
15 May 2011
TL;DR: In order to reduce power consumption and improve low-voltage operation capability of standard three transistor (3T) CMOS active pixel sensor (APS), new pixel readout is proposed utilizing supply boosting technique (SBT).
Abstract: In order to reduce power consumption and improve low-voltage operation capability of standard three transistor (3T) CMOS active pixel sensor (APS), new pixel readout is proposed utilizing supply boosting technique (SBT). Pixel supply voltage as well as reset and select signals for APS pixel are boosted to achieve wider and extended linear operating range in a standard CMOS process with high-Vt transistors. Reset and supply boosting was used for extending dynamic range of the pixel source follower (PSF) amplifier, while the select signal boosting was utilized for linearizing transfer characteristics of the PSF. Extension of PSF dynamic range using reset, select, and supply boosting (RSSB) resulted in operation of 3T APS pixel at 1.2V supply with 150mV dynamic range even though the threshold of the NMOS device was 0.8V. Proposed method does not degrade the device reliability margins and use single supply input.

6 citations


Cites background from "Electrical property modelling of ph..."

  • ...This increase could be as large as 50% of the zero threshold voltage for these devices [12] effecting linear input output characteristics of the PSF....

    [...]


Journal ArticleDOI
01 Dec 2017
Abstract: A new pixel is designed with the capability of imaging and energy harvesting for the retinal prosthesis implant in 0.18 µm standard Complementary Metal Oxide Semiconductor technology. The pixel conversion gain and dynamic range, are 2.05 $$\upmu{\text{V}}/{\text{e}}^{ - }$$ and 63.2 dB. The power consumption 53.12 pW per pixel while energy harvesting performance is 3.87 nW in 60 klx of illuminance per pixel. These results have been obtained using post layout simulation. In the proposed pixel structure, the high power production capability in energy harvesting mode covers the demanded energy by using all available p-n junction photo generated currents.

3 citations


Journal ArticleDOI
TL;DR: 4T CMOS APS shown more radiation hardness than the 3T CMos APS and 32 nm technology exhibits lowest radiation-tolerant, indicating 4T has a higher radiation hardness.
Abstract: The widely used CMOS Active Pixel Sensors (APS) in space imaging mission are vulnerable to radiations known as Single Event Transient (SET). This paper focus on 3T and 4T CMOS APS with tech...

3 citations


Cites methods from "Electrical property modelling of ph..."

  • ...This AC source is used by assuming the light is continuously hitting this photo-detector at a constant period (Ay 2005)....

    [...]


References
More filters

Journal ArticleDOI
Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

1,133 citations


Journal Article
Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

693 citations


Journal ArticleDOI
Abstract: The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.

544 citations


"Electrical property modelling of ph..." refers background in this paper

  • ...Threshold voltage and other physical parameters of MOS transistor are well defined and modeled for circuit simulators [3,4,5]....

    [...]


Journal ArticleDOI
TL;DR: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation, which allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling.
Abstract: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I/sub ds/, conductances and their derivatives throughout all V/sub gs/, V/sub ds/, and T/sub bs/, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on.

173 citations


"Electrical property modelling of ph..." refers background or methods in this paper

  • ...Threshold voltage and other physical parameters of MOS transistor are well defined and modeled for circuit simulators [3,4,5]....

    [...]

  • ...Threshold voltage of an NMOS transistor is given in (1), [3]....

    [...]

  • ...In this research [2], few electrical parameters of photodiode (PD) type CMOS Active Pixel Sensor (APS) pixel were modelled for hand calculation by using modified BSIM3v3 model equations [3]....

    [...]

  • ...A hybrid MOS threshold model equation was proposed [2] based on BSIM3v3 model equations [3] for simple and accurate representation of back-gate bias effect on the threshold voltage....

    [...]


01 Jan 1994
TL;DR: The Philips MOS MODEL 9 is presented with the successful confrontation with analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators.
Abstract: Analog applications of MOS transistors in integrated circuits impose enhanced requirements on the compact MOS models used in circuit simulators. Here we present for the Philips MOS MODEL 9 the successful confrontation with these analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators.<>

42 citations


"Electrical property modelling of ph..." refers background in this paper

  • ...Threshold voltage and other physical parameters of MOS transistor are well defined and modeled for circuit simulators [3,4,5]....

    [...]