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The AMchip04 and the processing unit prototype for the FastTracker

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TLDR
The first prototype of a new Processing Unit (PU) is presented, the core of the FastTracker processor (FTK), a real time tracking device for the ATLAS experiment`s trigger upgrade.
Abstract
Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment`s complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive event selection. We present the first prototype of a new Processing Unit (PU), the core of the FastTracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment`s trigger upgrade. The computing power of the PU is such that a few hundred of them will be able to reconstruct all the tracks with transverse momentum above 1 GeV/c in ATLAS events up to Phase II instantaneous luminosities (3 × 1034 cm−2 s−1) with an event input rate of 100 kHz and a latency below a hundred microseconds. The PU provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the ``combinatorial challenge'', is solved by the Associative Memory (AM) technology exploiting parallelism to the maximum extent; it compares the event to all pre-calculated ``expectations'' or ``patterns'' (pattern matching) simultaneously, looking for candidate tracks called ``roads''. This approach reduces to a linear behavior the typical exponential complexity of the CPU based algorithms. Pattern recognition is completed by the time data are loaded into the AM devices. We report on the design of the first Processing Unit prototypes. The design had to address the most challenging aspects of this technology: a huge number of detector clusters (``hits'') must be distributed at high rate with very large fan-out to all patterns (10 Million patterns will be located on 128 chips placed on a single board) and a huge number of roads must be collected and sent back to the FTK post-pattern-recognition functions. A network of high speed serial links is used to solve the data distribution problem.

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Journal ArticleDOI

AM06: The Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

TL;DR: The AM06 chip as mentioned in this paper is a parallel processor for pattern recognition in the ATLAS high energy physics experiment, which can store up to 131 072 patterns and has a memory bank that stores data organized in 18 bit words.
Proceedings ArticleDOI

Associative Memory for L1 track triggering in LHC environment

TL;DR: In this paper, the authors proposed a solution at the LHC for track reconstruction at level-1 in the HL-LHC upgrade, for very high-luminosity conditions (hundreds proton-proton collisions every 25 ns, at 5×1034 cm-2 sec-1).
Journal ArticleDOI

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

TL;DR: The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking.
Proceedings ArticleDOI

Characterisation of an Associative Memory Chip for high-energy physics experiments

TL;DR: This paper presents the approach used to characterize an Associative Memory Chip (AMChip) designed for the trigger systems of high-energy physics experiments in the Large Hadron Collider at CERN.
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Posted Content

Expected Performance of the ATLAS Experiment - Detector, Trigger and Physics

Georges Aad, +2604 more
TL;DR: In this article, a detailed study of the expected performance of the ATLAS detector is presented, together with the reconstruction of tracks, leptons, photons, missing energy and jets, along with the performance of b-tagging and the trigger.
Journal ArticleDOI

Performance of the ATLAS detector using first collision data

Georges Aad, +3256 more
TL;DR: In this paper, the performance of the ATLAS detector in the first half a million minimum bias events of the LHC collision data was investigated at center-of-mass energies of 0.9 TeV and 2.36 TeV.
Journal ArticleDOI

Triggering at LHC experiments

TL;DR: In this paper, the LHC design luminosity of 10 34 cm −2 s −1, an average of 17 events occurs at the beam crossing frequency of 25 ns, which must be reduced by a factor of at least 10 7 to about 100 Hz.
Proceedings ArticleDOI

Associative memory design for the fast track processor (FTK) at ATLAS

TL;DR: A new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments is proposed, which maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.
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