Journal ArticleDOI
The Effects of Interconnections on High-Speed Logic Circuits
TLDR
It is shown that high-speed circuitry must be miniaturized and the implications are discussed.Abstract:
By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed.read more
Citations
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Proceedings ArticleDOI
Analysis of Multiconductor Transmission Lines
T. B. Arabi,T. K. Sarkar +1 more
TL;DR: In this paper, the authors outline a methodology for the computation of the response of a multiconductor transmission line terminated by linear networks, where the lines are embedded in a multilayered lossy dielectric media and have arbitrary cross sections, but uniform along the length.
Journal ArticleDOI
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Yehea Ismail,Eby G. Friedman +1 more
TL;DR: The importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale, as the error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling.
Book
Time-Domain Response of Multiconductor Transmission Lines
TL;DR: In this paper, several techniques for the computation of the line response, starting from the known circuit-theory parameters, are presented and evaluated, such as time-stepping solution of the telegrapher equations, modal analysis in the time domain, model analysis in frequency domain, and a convolution technique which uses line Green's functions.
Journal ArticleDOI
Figures of merit to characterize the importance of on-chip inductance
TL;DR: In this article, a closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented, based on the alpha power law for deep submicrometer technologies.
Journal ArticleDOI
Equivalent Elmore delay for RLC trees
TL;DR: Closed-form solutions for the 50% delay, rise time, overshoots, and settling time of signals in an RLC tree are presented and have significantly improved accuracy as compared to the Elmore delay for an overdamped response.
References
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Proceedings ArticleDOI
Design of Univac®-LARC system: II
TL;DR: The engineering design of the LARC solid-state computer was a monumental challenge and resulted in a computer that revolutionised the way that information is stored and processed.
Journal ArticleDOI
Multilayer Etched Laminates: A New Packaging Design Tool
N. Schuster,W. Reimann +1 more
Journal ArticleDOI
UNIYAC-LARC High-Speed Circuitry: Case History in Circuit Optimization
TL;DR: This paper will discuss how circuit optimization techniques and use of the UNIVAC® I computing system aided in reducing cost and avoiding many of the pitfalls in the design and production of efficient high-speed circuitry for UNIVac-LARC.