Showing papers on "Channel length modulation published in 2013"

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

Abstract: This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.

Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

Abstract: As the MOSFET is scaled into a nanoscale regime, spreading of source/drain (S/D) dopant into the channel region will facilitate the lateral electric field spread into the channel and in turn deteriorate the gate electrostatic integrity. The short channel effects and performance are aggravated with the increase in lateral straggle (σL) of S/D Gaussian profile. In this paper, we have developed an analytical potential model that includes the effect of σL. Subsequently, an expression for threshold voltage and linear/saturation region drain current is proposed and the effect of σL over the transconductance (gm), output conductance (gds), and intrinsic gain (AV0) is studied.

An Analytical Threshold Voltage Model for Triple-Material Cylindrical Gate-All-Around (TM-CGAA) MOSFETs

Abstract: In this paper, an analytical threshold voltage model is proposed for a triple-material cylindrical gate-all-around MOSFET considering parabolic approximation of the potential along the radial axis. The center (axial) and the surface potential models are obtained by solving the 2-D Poisson's equation in the cylindrical coordinate system. This paper refutes the estimation of the natural length using surface potential as in previous work and proposes the use of center-potential-based natural length formulation for an accurate subthreshold analysis. The developed center potential model is used further to formulate the threshold voltage model and also extract drain-induced barrier lowering (DIBL) from the same. The effects of the device parameters like the cylinder diameter, oxide thickness, gate length ratio, etc., on the threshold voltage and DIBL are also studied in this paper. The model is verified by the simulations obtained from 3D numerical device simulator Sentaurus from Synopsys.

Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices

Abstract: InGaAs channel MOSFET devices with a channel thickness down to 3nm were fabricated and systematically characterized. Thinner channels result in improved electrostatics, however, the mobility rapidly drops to 110 cm2/Vs for the 3nm thick channel which results in significant loss of the drive current. 10 nm was found to be the optimum channel thickness with 77 mV/dec sub-threshold swing (SS). To account for the band-mixing and nonparabolicity of the III-V systems, 8-bands k.p simulations were conducted to gain an accurate insight into the device operation. As also verified experimentally, simulations suggest that the accumulation capacitance value increases as the channel thickness decreases due to the variations in the inversion charge profile. Simulations suggest that the InP buffer response affects the effective mass of the carriers and reduces the mobility as the channel becomes thinner. Based on this work, InGaAs channel thicknesses of 5nm and below hit severe performance issues.

CMOS Small-Signal and Thermal Noise Modeling at High Frequencies

Abstract: In this paper, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths. For the first time, approaches for excess noise factor modeling are validated versus measurements. Furthermore, important RF CMOS figures of merit are examined over many CMOS generations. With the scaling of CMOS technology, optimum RF performance is shown to be shifted from higher moderate toward lower moderate inversion, providing important guidelines for RFIC design. The results are validated with the charge-based EKV3 compact model, which considers short-channel effects such as channel length modulation, velocity saturation, and carrier heating.

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

Abstract: In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I ds), transconductance (g m), and cutoff frequency (f t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g ds) and higher early voltage (V ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.

On the Origin of Kink Effect in Current–Voltage Characteristics of AlGaN/GaN High Electron Mobility Transistors

Abstract: An explanation for the observed drain current collapse in AlGaN/GaN high electron mobility transistors is presented. The drain current-voltage (I-V) characteristics which show this undesirable behavior have been modeled using the physics-based ATLAS device simulator by Silvaco. A basic theory for the determination of virtual gate length for a three terminal device has been developed and used in the simulation. The simulated I-V characteristics closely match the experimental results. This paper suggests a model based on formation of a high resistance region under the virtual gate in the 2-D electron gas channel. The resistance of this region changes abruptly at a critical lateral electric field due to application of drain-source voltage. This abrupt change has been found to be a function of channel temperature. The dynamic behavior of this high resistance region has been proposed to be the cause of drain current collapse.

High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator tri-gate MOSFETs with high short channel effect immunity and V th tunability

Abstract: We have investigated the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. It was found that body thickness (Tbody) scaling provides better SCEs control, whereas Tbody scaling causes the reduction of the mobility limited by channel thickness fluctuation (δTbody) scattering (μfluctuation). To achieve better SCEs control, the thickness of channel layer (Tchannel) scaling is more favorable than the thickness of MOS interface buffer layer (Tbuffer) scaling, indicating necessity of quantum well (QW) channel structure. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/um. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control.

CNTFET: The emerging post-CMOS device

Abstract: This Paper presents the comparison of MOSFET and CNTFET devices. Many problems are associated with conventional MOSFET in nanometer regime. In this paper we have analyzed and justify why CNTFET is to be a post-CMOS device. For that we have analyzed the quantum capacitance and found that in CNTFET device it decreases with decrease in oxide thickness whereas in MOSFET device it increases, which leads to performance degradation of the device. After that we have observed from the HSPICE simulation that beyond 10 nm channel length the threshold voltage of MOSFET device is reduces rapidly whereas in CNTFE device it increases sharply which leads to reduce leakage power.

New methodology for drain current local variability characterization using Y function method

Abstract: Y function is well known to overcome the influence of source/drain series resistance (Rsd) in MOSFETs. In this work we present a new methodology for drain current local variability characterization using Y function method. Thus, we show that the study of Y function statistical variability permits the extraction of threshold voltage (VTH) and current gain factor (β) local variability without the influence of Rsd values. We also demonstrate a simple drain current local variability model taking into account the influence of Rsd and its variability in strong inversion regime. This new VTH and β extraction method, and drain current variability model were applied with success to advanced FDSOI and Bulk devices with different dimensions.

2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design

Abstract: Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance.

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

Abstract: An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and saturation regions of device operation. The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect. Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated. The model results are validated by numerical simulation results obtained by using the commercially available ATLAS™, a two dimensional device simulator from SILVACO.

Compact drain-current model for undoped cylindrical surrounding-gate metal-oxide-semiconductor field effect transistors including short channel effects

Abstract: In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

A propagation concept of negative bias temperature instability along the channel length in p-type metal oxide field effect transistor

Abstract: Combining simultaneously on the fly interface-trap (OTFIT) and the reverse voltage variation of source and drain (S/D) during measurement phase of measure/stress/measure (MSM) sequences, we have been able to scan the negative bias temperature instability (NBTI) across the channel length of PMOS transistors. In addition, we have analyzed the generation and evolution of interface-trap distribution with respect to the transistor gate length. We have found that NBTI-induced interface-trap density, Δ N it are not uniform along the channel. The experimental results reveal an evident propagation of the NBTI degradation. This propagation starts from S/D channel edges and penetrates into the channel center. It is accelerated by temperature and electric field until saturation. However, field-accelerated propagation seems more important than temperature-accelerated one. Further, transistors with shorter channel length degrade more rapidly than those with longer channel length. We have also shown that the channel length has a great effect on NBTI features such as the apparent activation energy and time power-law exponent. These results suggest that diffusion-limited process is not the sole source of the time degradation dependence, but also gate length have to be taken into account.

Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

Abstract: In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (Vds) and substrate (Vbs) voltages variation on DIBL is discussed. The dependency of channel length variation (ΔL), junction depth (rj), and substrate impurity concentration (NB) on DIBL is analyzed, and new equations are obtained. The evaluation results for the proposed model using MATHEMATICA give good agreement when compared with analytical and simulation results for BSIM4 level 54 and recent well-known models using HSPICE simulator.

Modeling of the impact of source/drain regions on short channel effects in MOSFETs

Abstract: This paper investigates the impact of the source/drain regions of MOSFETs on the short channel effects, by using numerical simulations as well as analytical modeling. First, the evidence of different SCEs when including or excluding S/D regions is presented using drift-diffusion simulation. It is then shown that this difference is related to the different boundary conditions used in the simulations. This different behavior is then modeled in terms of a shift in the built-in potential at the channel-S/D junction, which allows to avoid the overestimation of the SCEs, while keeping the same analytical modeling framework.

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

Abstract: This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence of the length close to the drain (L2). On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L2 and L1, although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation.

CMOS RF noise, scaling, and compact modeling for RFIC design

Abstract: This work presents an analysis of high frequency noise and linearity performance of a 90 nm CMOS process. Measurements are performed for a wide range of nominal gate lengths and bias points at high frequency. Modeling is based on the EKV3 compact model in Spectre RF circuit simulator from Cadence. The model shows correct scalability for noise and linearity accounting for short channel effects (SCEs), such as velocity saturation (VS) and channel length modulation (CLM). Results are presented versus a common measure of channel inversion level, named inversion coefficient. Optimum performance is shown to gradually shift from higher to lower levels of moderate inversion, when scaling from 240 nm to 100 nm. The same trend is observed from investigating the transconductance frequency product (TFP) of a common-source (CS) LNA for technology nodes ranging from 180 nm to 22 nm.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

Abstract: A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Long channel carbon nanotube as an alternative to nanoscale silicon channels in scaled MOSFETs

Abstract: Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metaloxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density.

Multiple-gate silicon on insulator (SOI) MOSFETs: Device design and analysis

Abstract: This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is a fundamental device in the development of very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase in effective number of gates. It minimizes short-channel effect which arises due to the lines of electric field from source and drain affecting control of the channel region. The technologies like Double-gate (top and bottom gate) SOI MOSFET and the Gate-all-Around (GAA) helps to suppress various short channel effects like Drain-Induced Barrier Lowering (DIBL) and degradation in Subthreshold slope. Nano MOSFETs are now the requirements of nano electronics and it is the Gate-all-Around MOSFET which is employed in silicon Nano wires.

Low-power-source-dependency band-gap reference voltage circuit design based on PTAT current

Abstract: The invention discloses the low-power-source-dependency band-gap reference voltage circuit design based on the PTAT current. The low-power-source-dependency band-gap reference voltage circuit design comprises a starting circuit, a reference voltage generating circuit and a reference buffering output circuit, wherein the reference voltage generating circuit is composed of three parts including a cascode current mirror circuit, a positive temperature coefficient PTAT current generating circuit and a negative temperature coefficient current generating circuit. The starting circuit is used for starting the reference voltage generating circuit after being powered on. The reference buffering circuit is used for reducing the output resistance to drive a low-resistance load and meanwhile providing various voltage references. According to the low-power-source-dependency band-gap reference voltage circuit design based on the PTAT current, the cascode PTAT current generating circuit is used for being coordinated with an external circuit to generate the reference voltage with the stable performance and the zero temperature coefficient, and meanwhile the method of separating an external power source from the bias voltage required by the circuit is used for greatly reducing the power source dependency caused by the channel length modulation effect of an MOS device.

Modeling of the effect of uniaxial mechanical strain on drain current and threshold voltage of an n-type MOSFET

Abstract: A semi-analytical model for evaluating the drain current in long channel n-type metal gate strained-Si MOSFET has been developed in this paper. An uniaxial compressive strain has been applied mechanically over the gate of the transistor. Depletion charge density, flat-band voltage and threshold voltage under the applied uniaxial compressive strain conditions have also been calculated. The flat-band voltage and the threshold voltage fall with the applied uniaxial compressive strain. There is a tremendous increase in the drain current under the applied strain. The drain current rises mainly due to the decrease in the optical band-gap of the silicon substrate material giving rise to the electron mobility due to decrease in the electron mass and the fall in the threshold voltage under the application of the strain. The results obtained for the drain current and the threshold voltage have also been compared with the reported experimental results. The modeled results match closely with reported results.

Cell protection system

Abstract: A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current MOSFET has a drain and a gate common with discharge control MOSFET. The charge current detection resistances and the discharge current detection resistance are provided in correspondence to the charge current detection MOSFET and the discharge current detection MOSFET, respectively. The control circuit generates a gate control signal for the charge control MOSFET and the charge current detection MOSFET by using the charge current detection resistance and generates a gate control signal for the charge control MOSFET and the discharge current detection MOSFET by using the discharge current detection resistance.

Performance enhancement and reduction of short channel effects of nano-MOSFET by using graded channel engineering

Abstract: The effect of the structure on electrical parameters of short channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors (DG MOSFETs) has been explored. To quantitatively assess the nanoscale DG MOSFET's characteristics, the On current(I on ), Off current (I off ), Sub threshold Swing (SS), Threshold voltage (V th ), and Drain-Induced Barrier Lowering (DIBL) are numerically calculated for the device with different channel length (L). Based on our two dimensional simulation, it is found that, to get optimum device characteristics and suppress short channel effects (SCEs) of nanoscale DG MOSFETs, t si and t ox should be simultaneously scaled down with respect to L. Even if it gives good results for V th , the device suffers for high DIBL, SS and I off . To suppress further these parameters, channel engineering technique is used followed by reducing the doping concentration of Source and Drain(S/D). The parameter extraction and simulation have been done by using the commercially available device simulation software ATLAS.