Showing papers on "Chip published in 2017"

High-resolution non-destructive three-dimensional imaging of integrated circuits

Abstract: A recently developed computational imaging technique, X-ray ptychographic tomography, is used to study integrated circuits, and a 3D image of a processor chip with a resolution of 14.6 nm is obtained. As computer chips have become increasingly crammed with nanometre-scale devices and circuitry, new microscopy techniques that can resolve the smallest features are required to enable chip design and inspection. X-ray imaging is uniquely suited for non-destructive, high-resolution imaging and Mirko Holler et al. make use of a recently developed computational imaging technique, X-ray ptychography, to generate high-resolution three-dimensional images of integrated circuits. They test X-ray ptychography on a circuit with known features, and then apply it to an Intel processor chip manufactured in the 22-nanometre technology, obtaining detailed three-dimensional maps of the devices with a resolution down to 14.6 nanometres. This technique could be used to assist quality control during chip production. Modern nanoelectronics1,2 has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography3,4—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques5,6,7. Foreseeable developments in X-ray sources8, optics9 and detectors10, as well as adoption of an instrument geometry11 optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture

Abstract: The performance of large-scale graph processing suffers from challenges including poor locality, lack of scalability, random access pattern, and heavy data conflicts. Some characteristics of FPGA make it a promising solution to accelerate various applications. For example, on-chip block RAMs can provide high throughput for random data access. However, large-scale processing on a single FPGA chip is constrained by limited on-chip memory resources and off-chip bandwidth. Using a multi-FPGA architecture may alleviate these problems to some extent, while the data partitioning and communication schemes should be considered to ensure the locality and reduce data conflicts. In this paper, we propose ForeGraph, a large-scale graph processing framework based on the multi-FPGA architecture. In ForeGraph, each FPGA board only stores a partition of the entire graph in off-chip memory. Communication over partitions is reduced. Vertices and edges are sequentially loaded onto the FPGA chip and processed. Under our scheduling scheme, each FPGA chip performs graph processing in parallel without conflicts. We also analyze the impact of system parameters on the performance of ForeGraph. Our experimental results on Xilinx Virtex UltraScale XCVU190 chip show ForeGraph outperforms state-of-the-art FPGA-based large-scale graph processing systems by 4.54x when executing PageRank on the Twitter graph (1.4 billion edges). The average throughput is over 900 MTEPS in our design and 2.03x larger than previous work.

Fast, energy-efficient, robust, and reproducible mixed-signal neuromorphic classifier based on embedded NOR flash memory technology

Abstract: We have designed, fabricated, and tested a prototype mixed-signal, 28×28-binary-input, 10-ouput, 3-layer neuromorphic network based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory. Each array performs a very fast and energy-efficient analog vector-by-matrix multiplication, which is the bottleneck for signal propagation in neuromorphic networks. All functional components of the prototype circuit, including 2 synaptic arrays with 101,780 floating-gate synaptic cells, 74 analog neurons, and the peripheral circuitry for weight adjustment and I/O operations, have a total area below 1 mm2. Its testing on the MNIST benchmark set has shown a classification fidelity of 94.65%, close to the 96.2% obtained in simulation. The classification of one pattern takes 103× better than those of the 28-nm IBM TrueNorth digital chip for the same task at a similar fidelity. Estimates show that this performance may be further improved using a better neuron design and a more advanced memory technology, leading to a >102x advantage in speed and a >104x advantage in energy efficiency over the state-of-the-art purely digital circuits for classification of large, complex patterns. Experimental results for the chip-to-chip statistics, long-term drift, and temperature sensitivity show no evident showstoppers on the way toward practical deep neuromorphic networks with unprecedented performance.

The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

Abstract: The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10 −5 and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm 2 for the application in the Inner Barrel Layers and below 20 mW/cm 2 for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported.

Continuously tunable ultra-thin silicon waveguide optical delay line

Abstract: As light cannot be stopped or directly stored in any media, optical delay lines are usually used to temporally trap the optical signals. We report a wide-range continuously tunable optical delay line chip consisting of a ring resonator array and a Mach–Zehnder interferometer (MZI) switch array on the 60-nm-thick silicon waveguide platform. The ring delay line provides continuous delay tuning of more than 10 ps with a push–pull differential tuning method. The MZI switchable delay line provides digitally programmable delay tuning with a resolution of 10 ps upon reconfiguration of the MZI switches to establish different optical routing paths. Dual-stage MZI switches are used to ensure low crosstalk with an improved signal-to-noise ratio. The delay line chip can generate a maximum delay of >1 ns with an on-chip insertion loss of 12.4 dB. Optical pulse time-division multiplexing and quasi-arbitrary waveform generation are realized based on the delay line chip. These results represent a significant step towards the realization of highly reconfigurable optical signal processors enabled by optical delay manipulation with broad applications for optical communications and microwave photonics.

Rail-to-Rail-Input Dual-Radio 64-Channel Closed-Loop Neurostimulator

Abstract: A 64-channel 0.13- $\mu \text{m}$ CMOS system on a chip (SoC) for neuroelectrical monitoring and responsive neurostimulation is presented. The $\Delta \Sigma $ -based neural channel records signals with rail-to-rail dc offset at the input without any area-intensive dc-removing passive components, which leads to a compact 0.013-mm2 integration area of recording and stimulation circuits. The channel consumes 630 nW, yields a signal to noise and distortion ratio of 72.2 dB, a 1.13- $\mu $ Vrms integrated input-referred noise over 0.1–500 Hz frequency range, and a noise efficiency factor of 2.86. Analog multipliers are implemented in each channel with minimum additional area cost by reusing the multi-bit current-digital to analog converter that is originally placed for current-mode stimulation. The multipliers are used for compact implementation of bandpass finite impulse response filters, as well as voltage gain scaling. A tri-core low-power DSP conducts phase-synchrony-based neurophysiological event detection and triggers a subset of 64 programmable arbitrary-waveform current-mode stimulators for subsequent neuromodulation. Two ultra-wideband (UWB) wireless transmitters communicate to receivers located at 10 cm to 2 m distance from the implanted SoC with data rates of 10–46 Mb/s, respectively. An inductive link that operates at 1.5 MHz provides power to the SoC and is also used to communicate commands to an on-chip ASK receiver. The chip occupies 6 mm2 while consuming 1.07 and 5.44 mW with delay-based and voltage controlled oscillator-based UWB transmitters, respectively. The SoC is validated in vivo using epilepsy monitoring (seizure detection) and treatment (seizure suppression) experiments.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control

Abstract: This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 $\mu$ m CMOS technology, occupying a silicon area of 3.7 mm $^2$ . The chip dissipates 56 $\mu$ W/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing

Abstract: Demand for highly energy-efficient coprocessor for the inference computation of deep neural networks is increasing. We propose the time-domain neural network (TDNN), which employs time-domain analog and digital mixed-signal processing (TDAMS) that uses delay time as the analog signal. TDNN not only exploits energy-efficient analog computing, but also enables fully spatially unrolled architecture by the hardware-efficient feature of TDAMS. The proposed fully spatially unrolled architecture reduces energy-hungry data moving for weight and activations, thus contributing to significant improvement of energy efficiency. We also propose useful training techniques that mitigate the non-ideal effect of analog circuits, which enables to simplify the circuits and leads to maximizing the energy efficiency. The proof-of-concept chip shows unprecedentedly high energy efficiency of 48.2 TSop/s/W.

Design and fabrication of a scalable liver-lobule-on-a-chip microphysiological platform.

Abstract: The design and fabrication of a very large-scale liver-lobule (VLSLL)-on-a-chip device, providing a microphysiological niche for hepatocytes, is described. The device consists of an integrated network of liver-lobule-like hexagonal tissue-culture chambers constructed in a hybrid layout with a separate seed-feed network. As a key feature, each chamber contains a central outlet mimicking the central vein of a liver lobule. Separating chamber walls located between the culture area and feed network protects cells from the shear force of the convective flow. Arrays of designated passages convey nutrients to the cells by diffusion-dominated mass transport. We simulated the flow velocity, shear stress and diffusion of glucose molecules inside and outside the culture chambers under a continuous flow rate of 1 μl min-1. As proof of concept, human hepatocellular carcinoma cells (HepG2) were cultured for periods of 5 and 14 days and human-induced pluripotent stem cell (hiPSC)-derived hepatocytes for 21 days. Stabilized albumin secretion and urea synthesis were observed in the microfluidic devices and cells maintained morphology and functionality during the culture period. Furthermore, we observed 3D tissue-like structure and bile-canaliculi network formation in the chips. Future applications of the described platform include drug development and toxicity studies, as well as the modeling of patient-specific liver diseases, and integration in multi-organ human-on-a-chip systems.

Endowing a plain fluidic chip with micro-optics: a holographic microscope slide.

Abstract: Lab-on-a-Chip (LoC) devices are extremely promising in that they enable diagnostic functions at the point-of-care Within this scope, an important goal is to design imaging schemes that can be used out of the laboratory In this paper, we introduce and test a pocket holographic slide that allows digital holography microscopy to be performed without an interferometer setup Instead, a commercial off-the-shelf plastic chip is engineered and functionalized with this aim The microfluidic chip is endowed with micro-optics, that is, a diffraction grating and polymeric lenses, to build an interferometer directly on the chip, avoiding the need for a reference arm and external bulky optical components Thanks to the single-beam scheme, the system is completely integrated and robust against vibrations, sharing the useful features of any common path interferometer Hence, it becomes possible to bring holographic functionalities out of the lab, moving complexity from the external optical apparatus to the chip itself Label-free imaging and quantitative phase contrast mapping of live samples are demonstrated, along with flexible refocusing capabilities Thus, a liquid volume can be analyzed in one single shot with no need for mechanical scanning systems

Terahertz Wireless Data Transmission With Frequency and Polarization Division Multiplexing Using Resonant-Tunneling-Diode Oscillators

Abstract: High-capacity short-distance wireless communications in the terahertz (THz) range are anticipated and therefore have been intensively studied. Higher data rates are made possible by the introduction of frequency division multiplexing (FDM) and polarization division multiplexing (PDM) schemes in the THz range. In this paper, wireless data transmissions using 2-channel FDM in the 500 and 800 GHz ranges and PDM in the 500 GHz range are demonstrated using resonant-tunneling-diode oscillators with different frequencies and polarizations integrated into one chip. Transmissions at a data rate of 28 Gbit/s were achieved in each channel with an error rate below the forward error correction limit in both multiplexing systems. The ratios of the leakage of the transmitted signal in one channel into the other channel were about −40 and −30 dB in FDM and PDM modes, respectively.

Demonstration of a compressive-sensing Fourier-transform on-chip spectrometer.

Abstract: We demonstrate compressive-sensing (CS) spectroscopy in a planar-waveguide Fourier-transform spectrometer (FTS) device. The spectrometer is implemented as an array of Mach–Zehnder interferometers (MZIs) integrated on a photonic chip. The signal from a set of MZIs is composed of an undersampled discrete Fourier interferogram, which we invert using l1-norm minimization to retrieve a sparse input spectrum. To implement this technique, we use a subwavelength-engineered spatial heterodyne FTS on a chip composed of 32 independent MZIs. We demonstrate the retrieval of three sparse input signals by collecting data from restricted sets (8 and 14) of MZIs and applying common CS reconstruction techniques to this data. We show that this retrieval maintains the full resolution and bandwidth of the original device, despite a sampling factor as low as one-fourth of a conventional (non-compressive) design.

Self-corrected chip-based dual-comb spectrometer.

Abstract: We present a dual-comb spectrometer based on two passively mode-locked waveguide lasers integrated in a single Er-doped ZBLAN chip. This original design yields two free-running frequency combs having a high level of mutual stability. We developed in parallel a self-correction algorithm that compensates residual relative fluctuations and yields mode-resolved spectra without the help of any reference laser or control system. Fluctuations are extracted directly from the interferograms using the concept of ambiguity function, which leads to a significant simplification of the instrument that will greatly ease its widespread adoption and commercial deployment. Comparison with a correction algorithm relying on a single-frequency laser indicates discrepancies of only 50 attoseconds on optical timings. The capacities of this instrument are finally demonstrated with the acquisition of a high-resolution molecular spectrum covering 20 nm. This new chip-based multi-laser platform is ideal for the development of high-repetition-rate, compact and fieldable comb spectrometers in the near- and mid-infrared.

All-optical control of light on a graphene-on-silicon nitride chip using thermo-optic effect.

Abstract: All-optical signal processing avoids the conversion between optical signals and electronic signals and thus has the potential to achieve a power efficient photonic system. Micro-scale all-optical devices for light manipulation are the key components in the all-optical signal processing and have been built on the semiconductor platforms (e.g., silicon and III-V semiconductors). However, the two-photon absorption (TPA) effect and the free-carrier absorption (FCA) effect in these platforms deteriorate the power handling and limit the capability to realize complex functions. Instead, silicon nitride (Si3N4) provides a possibility to realize all-optical large-scale integrated circuits due to its insulator nature without TPA and FCA. In this work, we investigate the physical dynamics of all-optical control on a graphene-on-Si3N4 chip based on thermo-optic effect. In the experimental demonstration, a switching response time constant of 253.0 ns at a switching energy of ~50 nJ is obtained with a device dimension of 60 μm × 60 μm, corresponding to a figure of merit (FOM) of 3.0 nJ mm. Detailed coupled-mode theory based analysis on the thermo-optic effect of the device has been performed.

A 76- to 81-GHz Multi-Channel Radar Transceiver

Abstract: This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars. The chip contains a two-channel transmitter (TX), a six-channel receiver (RX), a local-oscillator (LO) chain, and built-in self-test (BIST) circuitry. Each transmit channel includes multiple variable-gain amplifiers and a two-stage power amplifier. Measured on-die output power per channel is +18 dBm at 25 °C, decreasing to +16 dBm at 125 °C. Each receive channel includes a current-mode mixer, followed by intermediate-frequency buffers. At 25 °C, measured on-die noise figure is 10–11 dB, conversion gain is 14–15 dB, and input 1-dB compression point exceeds +1 dBm. An integrated LO chain drives the transmit and receive chains and includes an 18.5- to 20.6-GHz voltage-controlled oscillator connected to cascaded frequency doublers and a divide-by-four prescaler. At 25 °C, measured phase noise is −100 dBc/Hz at 1-MHz offset from a 77-GHz carrier. Integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature. The chip is flip-chip packaged into a ball-grid array and extracted interconnect loss for the package is 1.5 to 2 dB. Total power consumption for the chip is 1.8 W from 3.3 V for a single-TX, six-RX mode.

Online Training of an Opto-Electronic Reservoir Computer Applied to Real-Time Channel Equalization

Abstract: Reservoir computing is a bioinspired computing paradigm for processing time-dependent signals. The performance of its analog implementation is comparable to other state-of-the-art algorithms for tasks such as speech recognition or chaotic time series prediction, but these are often constrained by the offline training methods commonly employed. Here, we investigated the online learning approach by training an optoelectronic reservoir computer using a simple gradient descent algorithm, programmed on a field-programmable gate array chip. Our system was applied to wireless communications, a quickly growing domain with an increasing demand for fast analog devices to equalize the nonlinear distorted channels. We report error rates up to two orders of magnitude lower than previous implementations on this task. We show that our system is particularly well suited for realistic channel equalization by testing it on a drifting and a switching channel and obtaining good performances.

Paper-Based Digital Microfluidic Chip for Multiple Electrochemical Assay Operated by a Wireless Portable Control System

Abstract: The printing and modular fabrication of a paper-based active microfluidic lab on a chip implemented with electrochemical sensors (ECSs) is developed and integrated on a portable electrical control system. The electrodes of a chip plate for active electrowetting actuation of digital drops and an ECS for multiple analysis assays are fabricated by affordable printing techniques. For enhanced sensitivity of the sensor, the working electrode is modified through the electrochemical method, namely by reducing graphene with voltammetry and coating gold nanoparticles by amperometry. Detachable sensor and absorber modules are assembled modularly on an open chip plate, forming various novel hybridized open–closed chip formats. By varying the coupled or decoupled sensor modules, excellent detection of three diagnostic biological molecules is demonstrated (glucose, dopamine, and uric acid in human serum). With a newly designed portable power supply and wireless control system, the active paper-based chip platform can be utilized as an advanced point-of-care device for multiple assays in digital microfluidics.

A scalable self-priming fractal branching microchannel net chip for digital PCR

Abstract: As an absolute quantification method at the single-molecule level, digital PCR has been widely used in many bioresearch fields, such as next generation sequencing, single cell analysis, gene editing detection and so on. However, existing digital PCR methods still have some disadvantages, including high cost, sample loss, and complicated operation. In this work, we develop an exquisite scalable self-priming fractal branching microchannel net digital PCR chip. This chip with a special design inspired by natural fractal-tree systems has an even distribution and 100% compartmentalization of the sample without any sample loss, which is not available in existing chip-based digital PCR methods. A special 10 nm nano-waterproof layer was created to prevent the solution from evaporating. A vacuum pre-packaging method called self-priming reagent introduction is used to passively drive the reagent flow into the microchannel nets, so that this chip can realize sequential reagent loading and isolation within a couple of minutes, which is very suitable for point-of-care detection. When the number of positive microwells stays in the range of 100 to 4000, the relative uncertainty is below 5%, which means that one panel can detect an average of 101 to 15 374 molecules by the Poisson distribution. This chip is proved to have an excellent ability for single molecule detection and quantification of low expression of hHF-MSC stem cell markers. Due to its potential for high throughput, high density, low cost, lack of sample and reagent loss, self-priming even compartmentalization and simple operation, we envision that this device will significantly expand and extend the application range of digital PCR involving rare samples, liquid biopsy detection and point-of-care detection with higher sensitivity and accuracy.

A planar dielectrophoresis-based chip for high-throughput cell pairing.

Abstract: This paper reports the design and fabrication of a planar chip for high-throughput cell trapping and pairing (more than 2400 single cell-cell pairs in a microwell array) in a 1 × 1.5 cm area by positive dielectrophoresis (p-DEP) within only several minutes. The p-DEP was generated by applying an alternating current signal on a novel two-pair interdigitated array (TPIDA) electrode. The TPIDA electrode not only enabled the planar chip to be incorporated with a most often used PDMS microfluidic channel, but also contributed to a high single cell-cell pairing efficiency up to 74.2% by decreasing the induced electric field during consecutive p-DEP trapping of two cell types. Furthermore, the paired cells in each microwell could be "pushed" together into a microbaffle by a liquid flow through a capillary-sized channel, resulting in single cell-cell contact. More importantly, the planar chip could be used repeatedly by a simple water cleaning process. The planar chip offers an effective way for high-throughput single cell-cell pairing, which could provide a facile platform for cell communication and a precise cell pairing step in cell fusion.

Sprinkler: Maximizing Resource Utilization in Many-Chip Solid State Disks

Abstract: Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, Sprinkler relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions (i.e., improves transactional-locality) by over-committing flash memory requests to specific resources. Our extensive experimental evaluation using a cycle-accurate large-scale SSD simulation framework shows that a many-chip SSD equipped with our Sprinkler provides at least 56.6% shorter latency and 1.8 ~ 2.2 times better throughput than the state-of-the-art SSD controllers. Further, it improves overall resource utilization by 68.8% under different I/O request patterns and provides, on average, 80.2% more flash-level parallelism by reducing half of the flash memory requests at runtime.

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

Abstract: Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

The MuPix System-on-Chip for the Mu3e Experiment

Abstract: Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay μ + → e + e − e + . Decay vertex position, decay time and particle momenta have to be precisely measured in order to reject both accidental and physics background. A silicon pixel tracker based on 50 μm thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1 T solenoidal magnetic field provides precise vertex and momentum information. The MuPix chip combines pixel sensor cells with integrated analog electronics and a periphery with a complete digital readout. The MuPix7 is the first HV-MAPS prototype implementing all functionalities of the final sensor including a readout state machine and high speed serialization with 1.25 Gbit/s data output, allowing for a streaming readout in parallel to the data taking. The observed efficiency of the MuPix7 chip including the full readout system is ⩾ 99 % in a high rate test beam.

Chip-based Brillouin radio frequency photonic phase shifter and wideband time delay.

Abstract: We report a chip-based true-time-delay unit based on stimulated Brillouin scattering that uses an on-off Brillouin gain of 52 dB to enable 4 ns delay over a bandwidth of 100 MHz and a phase shift of ∼200°. To verify these operations, we use a two-tap microwave filter configuration and observed changes in the free spectral range of the filter and shift in the spectrum of the filter. The realization of these functionalities on chip-scale devices is critical for phased-array antennas, multibeam satellites, delay lines, arbitrary waveform generation, and reconfigurable microwave photonic filters.

Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing

Abstract: A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF unit capacitors. The computation is digitized with a 6 b asynchronous successive approximation register analog-to-digital converter. The analyses of incomplete charge accumulation and thermal noise are discussed. The design was fabricated in 40 nm CMOS, and experimental measurements of multiplication are illustrated using matched filtering and image convolutions to analyze noise and offset. Two applications are highlighted: 1) energy-efficient feature extraction layer performing both compression and classification in a neural network for an analog front end and 2) analog acceleration for solving optimization problems that are traditionally performed in the digital domain. The chip obtains measured efficiencies of 8.7 TOPS/W at 1 GHz for the first application and 7.7 TOPS/W at 2.5 GHz for the second application.

Dual-Terahertz-Comb Spectrometer on CMOS for Rapid, Wide-Range Gas Detection With Absolute Specificity

Abstract: This paper describes the design and implementation of a 220–320 GHz spectrometer consisting of a pair of 65-nm CMOS chips. The spectrometer utilizes two counter-propagating frequency-comb signals to seamlessly scan the broadband spectrum and significantly reduces the total scanning time through high parallelism. The comb signal, with ten equally spaced frequency tones, is generated and detected by a chain of inter-locked transceivers on chip. The large reduction of required tuning range for each transceiver enables peak energy efficiency across a wide bandwidth. Each transceiver is based on a multi-functional electromagnetic structure, which serves as a frequency doubler, sub-harmonic mixer and an on-chip radiator simultaneously. In particular, theory and design methodology of a dual-transmission-line feedback scheme are presented, which maximizes the transistor gain near its cutoff frequency $f_{\mathrm{ max}}$ and enhances the harmonic generation efficiency. The spectrometer chip has a measured total radiated power of 5.2 mW and a measured single-sideband noise figure of 14.6 ~ 19.5 dB, representing the highest generated power and sensitivity of silicon-based terahertz circuits. The chip consumes a dc power of 1.7 W. Finally, absorption spectrum of acetonitrile (CH3CN) and carbonyl sulfide is obtained, which agree with the JPL spectroscopy catalog.

On the nanocommunications at THz band in graphene-enabled Wireless Network-on-Chip

Abstract: One of the main challenges towards the growing computation-intensive applications with scalable bandwidth requirement is the deployment of a dense number of on-chip cores within a chip package To this end, this paper investigates the Wireless Network-on-Chip (WiNoC), which is enabled by graphene-based nanoantennas (GNAs) in Terahertz frequency band We first develop a channel model between the GNAs taking into account the practical issues of the propagation medium, such as transmission frequency, operating temperature, ambient pressure, and distance between the GNAs In the Terahertz band, not only dielectric propagation loss but also molecular absorption attenuation (MAA) caused by various molecules and their isotopologues within the chip package constitutes the signal transmission loss We further propose an optimal power allocation to achieve the channel capacity The proposed channel model shows that the MAA significantly degrades the performance at certain frequency ranges compared to the conventional channel model, even when the GNAs are very closely located More specifically, at transmission frequency of 1 THz, the channel capacity of the proposed model is shown to be much lower than that of the conventional model over the whole range of temperature and ambient pressure of up to 268% and 25%, respectively

Pesticide vapor sensing using an aptamer, nanopore, and agarose gel on a chip.

Abstract: A pesticide vapor sensor was developed using an agarose gel-based chip containing a nanopore sensing system. Vaporized omethoate was detected by the absorption into the gel, the complex formation with a DNA aptamer, and its obstruction at the nanopore. This strategy is applicable to other vapors, expanding the versatility of nanopore sensors.