Showing papers on "Effective number of bits published in 2011"

A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

Abstract: This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 μm × 240 μm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 μW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.

A SAR-Assisted Two-Stage Pipeline ADC

Abstract: Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex We pro pose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC The prototype 12b 50 MS/s ADC achieves an ENOB of 104b at Nyquist, and a figure-of-merit of 52 f J/conversion-step The ADC achieves low-power, high-resolution and high-speed operation without calibration The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 016 mm2

A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit

Abstract: We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm2 and 0.02 mm2 respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems.

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

Abstract: This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.

An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications

Abstract: An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically seen in asynchronous ADCs. A prototype ADC fabricated in a 0.18 μm CMOS technology, and utilizing the subthreshold region of operation, achieves an equivalent maximum sampling rate of 50 kS/s, an SNDR of 43.2 dB, and consumes 25 μW from a 0.7 V supply. The ADC is also shown to provide data compression for accelerometer applications as a proof of concept demonstration.

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory

Abstract: Modern optical systems increasingly rely on DSP techniques for data transmission at 40Gbs and recently at 100Gbs and above. A significant challenge towards CMOS TX DSP SoC integration is due to requirements for four 6b DACs (Fig. 10.8.1) to operate at 56Gs/s with low power and small footprint. To date, the highest sampling rate of 43Gs/s 6b DAC is reported in SiGe BiCMOS process [1]. CMOS DAC implementations are constraint to 12Gs/s with the output signal frequency limited to 1.5GHz [2–4]. This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >30dBc and ENOB>4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die area is less than 0.6×0.4 mm2.

A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references

Abstract: This paper presents a fully-digital capacitive sensor interface. By directly transforming the sensor value instead of using an intermediate step in the voltage domain, the architecture can cope with very low signal swings. An implementation for barometric pressure sensing with a supply voltage of 0.3 V demonstrates the benefits. With a power consumption of only 270 nW and an acquisition time of 1 ms, an ENOB of 6.1 is obtained, resulting in a FOM of 2.1 pJ/conv for the entire interface. This is at least an order of magnitude better than current state-of-the-art implementations.

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

Abstract: This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-Vt MOSFETs. A 10-bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 μm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8 and ?0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices

Abstract: This paper describes an ultra-low-power SAR ADC in 0.13-μm CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-μm CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.

A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS

Abstract: A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110 μm × 105 μm. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing.

Threshold-Based Relaying in Coded Cooperative Networks

Abstract: In cooperative communications, error propagation at the relay nodes degrades the diversity order of the system. To combat that effect, we present a novel technique to control error propagation at the relays, which is implemented in the context of a distributed turbo code. In the presented technique, the relay calculates the log-likelihood ratio (LLR) values for the bits sent from the source. These values are subjected to a threshold to distinguish the reliable bits from the unreliable bits. The relay then forwards the bits that are deemed reliable and discards the bits that are not, resulting in fewer errors propagating to the destination. The assumption here is that the destination does not know the location of the discarded bits. We develop upper bounds on the end-to-end bit error rate, enabling us to optimize the threshold in terms of the minimum end-to-end bit error rate. We compare our technique with existing techniques that have been proposed to control error propagation, including using only a cyclic redundancy code check at the relay, forwarding analog LLR values, and by employing no error control at the relay at all. We demonstrate, through several numerical examples, that the proposed scheme outperforms all existing schemes.

Adaptive Resolution ADC Array for an Implantable Neural Sensor

Abstract: This paper describes an analog-to-digital converter (ADC) array for an implantable neural sensor which digitizes neural signals sensed by a microelectrode array. The ADC array consists of 96 variable resolution ADC base cells. The resolution of each ADC cell in the array is varied according to neural data content of the signal from the corresponding electrode. The resolution adaptation algorithm is essentially to periodically recalibrate the required resolution and this is done without requiring any additional ADC cells. The adaptation implementation and results are described. The base ADC cell is implemented using a successive approximation charge redistribution architecture. The choice of architecture and circuit design are presented. The base ADC has been implemented in 0.13 μm CMOS as a 100 kS/s SAR ADC whose resolution can be varied from 3 to 8 bits with corresponding power consumption of 0.23 μW to 0.90 μW achieving an ENOB of 7.8 at the 8-bit setting. The energy per conversion step figure of merit is 48 fJ/step at the 8-bit setting. Resolution adaptation reduces power consumption by a factor of 2.3 for typical motor neuron signals while maintaining an effective 7.8-bit resolution across all channels.

An offset cancellation technique for comparators using body-voltage trimming

Abstract: In this paper an offset cancellation technique based on body voltage trimming is presented to be used in the comparators employed in Flash or Successive-Approximation analog-to-digital converters. The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. The technique is employed in the design of a 6-bit 1-GSps Flash ADC in 0.18μm CMOS technology. Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28mV to 750μV operating at 1-GHz with only 25μW power in offset cancellation. The cancellation scheme generally improves the ENOB by approximately 0.5 bit after cancellation.

A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS

Abstract: A 7-bit 1.5-GS/s analog-to-digital converter (ADC) incorporates redundancy, reassignment, and digital correction to reduce the complexity of analog functions and the required accuracy compared to traditional Flash ADCs. Deliberate and random mismatch is used to set the desired trip points, achieving a 600-mVpp differential input signal range. The need for a low-impedance high-precision resistor reference ladder is eliminated, and comparator performance is decoupled from matching requirements, so that small and fast dynamic comparators can be used. New analysis discusses the optimum combination of random and deliberate comparator offset to achieve a target effective number of bits (ENOB). This prototype ADC has the highest ENOB and highest sampling frequency of any reported Flash ADC utilizing redundancy. A proof-of-concept prototype achieves no missing codes, 46.6-dB spurious-free dynamic range, and 6.05-bit ENOB at Nyquist input frequency. Fabricated in 90-nm digital CMOS, with a core area of 1.2 mm2, the device consumes 204 mW from a 1.2-V/0.9-V analog/digital supply.

Two-stage analog-to-digital converter using sar and tdc

Abstract: Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.

Multilayer decoding using persistent bits

Abstract: The invention relates to a method of iterative multi-layer decoding of a multimedia communication signal, wherein persistent bits from various upper layers of the employed protocol stack are used in error correction decoding at a lower error-correction layer. The method includes saving persistent bits from successfully decoded FEC frames in memory, and using a subset of the saved bits in decoding of future frames. A smart controller is used to analyze frames for the presence and location of persistent bits, for saving thereof in memory, and for inserting saved persistent bits into a next frame at successive decoding iterations thereof.

A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- $\mu\hbox{m}$ CMOS

Abstract: As the low-power-consumption requirement of integrated circuits for biomedical applications (e.g., wearable sensor nodes operating with and without batteries, and implantable medical devices powered by batteries and wireless charging) becomes more stringent, the data converter design evolves toward mircrowatt and submircrowatt power consumption. In this brief, a 400-nW successive approximation analog-to-digital converter (SAR ADC) is presented. A trilevel switching scheme with common-mode reset, redundant algorithm, and a time-domain comparator is proposed and implemented to achieve ultralow power consumption. The redundant algorithm mitigates the offset error caused by the level mismatch of the trilevel switching scheme, whereas the trilevel switching scheme simplifies the switching logic of the redundant algorithm. Fabricated in a 0.18-μm CMOS process, the proposed SAR ADC achieves a signal-to-noise-and-distortion ratio of 50 dB, which is equivalent to an 8-bit effective number of bits, at an 80-kS/s conversion rate. The figure of merit is 19.5 fJ/conversion step.

Non-volatile memory and methods with reading soft bits in non uniform schemes

Abstract: A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.

Photonic Time-Stretched Analog-to-Digital Converter Amenable to Continuous-Time Operation Based on Polarization Modulation With Balanced Detection Scheme

Abstract: In this paper, we show analytically and experimentally that a polarization modulator which supports TE and TM modes of opposite phase modulation indexes can be utilized to reject dispersion-induced even-order distortions in a photonic Time-Stretched Analog-to-Digital Converter (TS-ADC). The output of the polarization modulator propagates through a single dispersive channel. This makes the present scheme amenable to continuous operation. Based on the virtual time gating principle, the continuous-time RF signal is time-stretched by a factor of 4 and segmented into four channels prior to digitization. For a single channel, differential operation is achieved by using a polarization beam-splitter that generates complementary pulses which are fed to a balanced detector. The differential operation helps to reject dispersion-induced even-order distortions and the balanced detection assists in the suppression of second-order distortion as well as improving the signal-to-noise ratio (SNR) by 6 dB. Using a 10 bit electronic ADC with a sampling rate of 2 GSamples/s, we demonstrate digitization of RF signals up to a frequency of 950 MHz and obtain ~ 3.56 effective number of bits (ENOB) with a single channel at ~ 31.6% of the electronic ADC's peak-to-peak full scale voltage. With adequate backend digitizing hardware, a four-channel continuous-time TS-ADC with a sampling rate of 8 GSamples/s can be realized to handle RF frequencies as high as 4 GHz.

An ultra-low-power SAR ADC with an area-efficient DAC architecture

Abstract: An ultra-low-power area-efficient 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low-power performance a DAC architecture is proposed that employs two rail-to-rail low-power unity-gain buffers and only 4 minimum-size capacitors instead of the conventional binary-weighted capacitor array. Thereby, power consumption and area are drastically reduced by virtue of lower switching activity and smaller size capacitor array. The proposed 8-bit SAR ADC is designed and simulated in a 0.13µm CMOS process. Simulation results show that for a 2.4 kHz (12.4 kHz) input signal while sampling at 25 kHz, the ADC achieves an ENOB of 7.9 (7.8), consumes 290 nW (350 nW) form a 0.8 V analog supply and a 0.6 V digital supply, and achieves a FoM of 48 fJ/conversion-step (62 fJ/conversion-step).

A High-Performance Procedure for Effective Number of Bits Estimation in Analog-to-Digital Converters

Abstract: This paper deals with a procedure for high-accuracy fast estimation of the effective number of bits ( ENOB) of an analog-to-digital converter (ADC). According to this procedure the ADC output sine-wave parameters are determined through the interpolated discrete Fourier transform (IpDFT) method. One criterion for the selection of the window that will be used in the IpDFT method is provided. In addition, mathematical expressions for the accuracy of both the sine-fitting procedure based on the IpDFT method and the proposed ENOB estimation method are derived, and a lower bound on the number of acquired samples that ensures accurate ENOB estimates with a high confidence level is proposed. In particular, it is proved that the uncertainty of the proposed ENOB estimation procedure is almost the same as the theoretical lower bound for the variance of any unbiased ENOB estimator. Finally, the accuracy of the proposed procedure and the algorithms suggested in the existing standards for ADCs testing are compared through both computer simulations and experimental results. In addition, the processing times required by each considered method are compared, therefore proving the advantage of the proposed procedure in terms of the required computational burden.

A 10 b 50 MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs

Abstract: A 10 b opamp-sharing pipeline analog-to-digital (A/D) using current-reuse operational transconductance amplifiers (OTA) with dual nMOS differential inputs is presented. The current-reuse OTA topology facilitates opamp-sharing between all of the consecutive pipeline stages, minimizing power consumption and die area. Analog transistors in the OTA are always biased in saturation ensuring no loss of settling time due to OTA power turn-on delays. The A/D is fabricated in a 0.18-μ m CMOS process and occupies an active die area of 0.7 mm2. At 50 MS/s, maximum SNDR of 58 dB (ENOB=9.3 b) is achieved with 9.2 mW analog power consumption on a 1.8 V supply.

Low-power 4-bit flash analogue to digital converter for ranging applications

Abstract: A 4-bit 700 MS/s flash ADC is presented in 0.18 µm CMOS. By lowering the kickback noise of the individual comparators it was possible to reduce the power consumption to 4.43 mW. Improved calibration capabilities resulted in an INL and DNL smaller than 0.25 LSB. These low nonlinearities give rise to 3.77 effective number of bits at the Nyquist input frequency and this in turn yields an overall figure of merit of 0.46 pJ per conversion step, the lowest figure of merit reported for ADCs with sampling rate above 500 MHz in 0.18 µm CMOS.

A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC

Abstract: An open-loop interpolated pipeline ADC is proposed. Weight controlled capacitor arrays are introduced to realize an interpolation and a pipelined operation with open-loop amplifiers. The 10-bit ADC fabricated in 90 nm CMOS demonstrates ENOB of 8.5b over 80 MHz bandwidth (BW) and a conversion rate of 320 MS/s without linearity compensation and consumes 40 mW. The FoMs are 780 fJ/c.-s. defined by the 80 MHz BW and 390 fJ/c.-s. defined by the 320 MSps conversion rate with a BW of 80 MHz.

A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC

Abstract: Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using complex calibration techniques. A two-channel time-interleaved 5-bit asynchronous digital slope ADC was implemented in a 90-nm CMOS technology and occupies 160 μm × 200 μm. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1-V supply.

Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

Abstract: This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp analog-to-digital converter (ADC) for a small animal positron emission tomography(PET) imaging system. The proposed ADC is a part of a monolithic front-end readout application-specific integrated circuit(ASIC) which is dedicated to the detector modules consisting of LYSO scintillation crystals read out on both sides by the multi-channel plate (MCP) photodetectors. The function of the ADC is to digitize the voltage signals from a large number of readout channels. Digital delay-locked loop (DLL) techniques are proposed to realize time interpolations in order to reduce the conversion time and to enhance the resolution. Both high precision and low power are obtained. An eight-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The available resolution of the ADC is 9 ~ 12 bits. The maximum DNL and INL of the fine conversion in the ADC is ±0.75 LSB and ±0.5 LSB, respectively. The static power consumption of the ADC is 3 mW + 0.2 mW/Channel. This ADC architecture provides a possibility to integrate low-noise front-end readout circuits, time-to-digital converters and ADC together into a monolithic ASIC and to output both the energy quantity and the time information with digital representations for PET imaging systems.

Multilevel Power Optimization of Pipelined A/D Converters

Abstract: Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This paper presents a multilevel design optimization approach for reducing the power dissipation of a pipelined analog-to-digital converter (ADC). At the circuit-level, device-types and supply-voltages are jointly optimized for the residue amplifier of a pipeline stage to minimize power. At the architecture-level, the nonlinearity contribution from stage gain error is optimally distributed to further minimize combined power dissipation. The optimizations take advantage of an analytical optimization method based on geometric programming for a quantitative tradeoff analysis. All of the proposed power optimizations are applied to the design of a two-way interleaved 8-bit 320 MS/s pipelined ADC in 90-nm CMOS technology. Measured performance from a prototype chip shows 7.30-bit of ENOB at Nyquist input frequency with DNL of -0.35/+0.45 LSB and INL of -0.72/+0.89 LSB, while dissipating 12.77 mW from 2.1 V/1.2 V supplies. The achieved conversion efficiency is 253fJ/conv-step.

A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications

Abstract: A low-FOM SAR ADC using the leakage reduction bootstrapped switch (LRBS) to achieve a satisfactory ENOB and using a low-power approach with a low voltage, low sampling rate, and low-DAC-capacitance structure is presented for biomedical applications. LRBS is proposed to alleviate the leakage caused by the low-power approach to increase SNDR and ENOB. From the measurement results, the 0.18µm CMOS prototype chip with the total DAC capacitance of 2.765pF consumes 2.5nW and achieves a SNDR of 53.05dB under a 0.5V supply voltage at 1KS/s with a Nyquist input. The resulting FOM is 6.8fJ/conversion-step.

Zero-Crossing Detector Based Reconfigurable Analog System

Abstract: A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92 mW at 50 MSPS with ENOB of 8.02 bit and FOM of 150 fJ/conversion-step. A second-order and a third-order Butterworth filter are also demonstrated. The thermal noise of the system is analyzed in different configurations and the dominant sources of noise are determined. It is shown that around 90% of the noise in ADC configuration is generated by the first stage, while in filter configuration, around 90% of the noise is generated by the last stage. The chip is implemented in a 65 nm technology.

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

Abstract: This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. The proposed topology, when compared with previous binary-search ADC architectures, further reduces the number of comparators from 2N-1 to N for N-bit precision, the comparator structure is simplified, and it can avoid both the signal dependent offsets and the kickback noise. The proposed binary-search ADC has been implemented in 65nm CMOS process and it consumes 1.63mW at an operation frequency of 500MS/s. The measurement results demonstrate that the binary-search ADC achieves 30.7dB SNDR (4.8-bit ENOB).