Showing papers on "Gate driver published in 2019"

Active Gate-Driver With dv/dt Controller for Dynamic Voltage Balancing in Series-Connected SiC MOSFETs

Abstract: Series connection of individual semiconductors is an effective way to achieve higher voltage switches. However, the inherent unequal dynamic voltage sharing problem needs to be solved, even when well-matched gate drivers and semiconductors are used. A majority of the existing voltage balancing schemes are developed for slow-switching silicon (Si)-based semiconductors, and are also associated with a significant amount of additional losses in the control circuit or on the switches. In this paper, a novel method is proposed for balancing the dynamic voltages among series-connected silicon carbide (SiC) MOSFETs with high dv/dt rates. The method takes advantage of a small capacitor to provide additional current to the gate of the MOSFETs at turn- off , meaning the switching speed (and thus, the device voltage after turn- off ) is controlled. The proposed method generates negligible losses in the control circuit, and also does not significantly increase the switching losses of the semiconductors. Experimental results are provided to prove the effectiveness of the proposed voltage balancing scheme on two SiC MOSFETs inside a module connected in series. In order to do so, an active gate driver is designed embedding the active dv/dt control scheme as well as other essential functionalities needed for operation of SiC MOSFETs.

Design Considerations and Development of an Innovative Gate Driver for Medium-Voltage Power Devices With High $dv/dt$

Abstract: Medium-voltage (MV) silicon carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon-based IGBTs From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it However, when SiC devices are used in these applications, they are exposed to a high peak stress (5–10 kV) and a very high $dv/dt$ (10–100 kV/ $\mu$ s) Using these devices calls for a gate driver with a dc–dc isolation stage that has ultralow coupling capacitance in addition to be able to withstand the high isolation voltage This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver An MV isolation transformer is designed with a low interwinding capacitance, while maintaining the clearance, creepage, as well as insulation standards A dc isolation test has been performed to validate the integrity of the insulating material The key features include low input common mode current, and a short-circuit protection scheme specifically designed for 10 kV SiC mosfet s The performance of the gate driver is evaluated using double pulse tests and continuous tests Experimental results validate the advantages of the gate driver and its application for MV SiC devices exhibiting very high $dv/dt$ The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices

A Novel Active Gate Driver for Improving Switching Performance of High-Power SiC MOSFET Modules

Abstract: Featuring higher switching speed and lower losses, the silicon carbide mosfet s (SiC mosfet s) are widely used in higher power density and higher efficiency power electronic applications as a new solution. However, the increase of the switching speed induces oscillations, overshoots, electromagnetic interference (EMI), and even additional losses. In this paper, a novel active gate driver (AGD) for high-power SiC mosfet s is presented to fully utilize its potential of high-speed characteristic under different operation temperatures and load currents. The principle of the AGD is based on drive voltage decrement during the voltage and current slopes since high dV/dt and dI/dt are the source of the overshoots, oscillations, and EMI problems. In addition, the optimal drive voltage switching delay time has been analyzed and calculated considering a tradeoff between switching losses and switching stresses. Compared to conventional gate driver with fixed drive voltage, the proposed AGD has the capability of suppressing the overshoots, oscillations, and reducing losses without compromising the EMI. Finally, the switching performance of the AGD was experimentally verified on 1.2 kV/300 A and 1.7 kV/300 A SiC mosfet s in double pulse test under different operation temperatures and load currents. In addition, an EMI discussion and cost analysis were realized for AGD.

Non-isolated buck–boost dc–dc converter with quadratic voltage gain ratio

Abstract: A new transformer-less buck-boost converter is proposed, which owns a quadratic voltage gain ratio. The proposed converter (a) has only one active switch, which makes the implementation of the gate driver and control system simpler; (b) has a quadratic voltage gain without using a transformer, which equips the designers to obtain a high-voltage gain ratio and avoid the complexity of magnetic utilisations; (c) works both in step-up or step-down mode, while most of the existing quadratic topologies are able to work either in step-up or step-down mode; and (d) shares a common ground between the input and output terminals. The operating states of the proposed converter along with its steady-state performance are analysed. Then, the small-signal modelling and the power loss analysis are performed. A comparison shows the unique features of the converter, specifically in terms of voltage gain ratio and the count of power switches. Finally, the experimental results of a laboratory prototype, as well as the simulation results from PSIM software, are used for validation. The converter was tested in different conditions to inspect its transient response and to record its efficiency. The maximum recorded efficiencies in boost and buck modes, respectively were 94.7 and 93%.

Short-Circuit Characterization and Protection of 10-kV SiC mosfet

Abstract: This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet . The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μ s is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

A Fast-Switching Integrated Full-Bridge Power Module Based on GaN eHEMT Devices

Abstract: New packaging solutions and power module structures are required to fully utilize the benefits of emerging commercially available wide bandgap semiconductor devices. Conventional packaging solutions for power levels of a few kilowatt are bulky, meaning important gate driver and measurement circuitry are not properly integrated. This paper presents a fast-switching integrated power module based on gallium nitride enhancement-mode high-electron-mobility transistors, which is easier to manufacture compared with other hybrid structures. The structure of the proposed power module is presented, and the design of its gate driver circuit and board layout structure is discussed. The thermal characteristics of the designed power module are evaluated using COMSOL Multiphysics. An ANSYS Q3D Extractor is used to extract the parasitics of the designed power module, and is included in simulation models of various complexities. The simulation model includes the SPICE model of the gallium nitride devices, and parasitics of components are included by experimentally characterizing them up to 2 GHz. Finally, the designed power module is tested experimentally, and its switching characteristics cohere with the results of the simulation model. The experimental results show a maximum achieved switching transient of 64 V/ns and verify the power loop inductance of 2.65 nH.

In situ Condition Monitoring of IGBTs Based on the Miller Plateau Duration

Abstract: Aging precursor identification is crucial to achieving online condition monitoring and estimating the remaining lifetime of insulated-gate bipolar transistors (IGBTs). However, existing failure precursors are limited with respect to in situ monitoring. In this paper, the duration of the Miller plateau during the IGBT turn- on transition is proposed as an online precursor indicating two dominant types of failures. Based on the theoretical closed-form expressions, the adverse effects of package-related bond wire fatigue and chip-related gate oxide degradation on the Miller plateau duration are explained. By using a dedicated online measurement system that is implemented on the gate driver side, the proposed precursor is extracted during operation. Discrete IGBTs of two gate structures are employed during the accelerated aging tests. Negative and positive degradation trends of the Miller plateau duration under power cycling and high electric field stress, respectively, are revealed, thus illustrating the validity of the proposed method. Finally, the main differences in physics-of-failure between two types of aged devices are investigated using post-failure analysis. The innovation of applying the Miller plateau duration as a failure precursor involves its ability to accomplish real-time field monitoring and its sensitivity to multiple failure mechanisms.

A Compact Series-Connected SiC MOSFETs Module and Its Application in High Voltage Nanosecond Pulse Generator

Abstract: Nanosecond pulse discharge plasma has many prospects in industrial applications, and high-voltage repetitive nanosecond pulse generators with compact design and light weight have become one of the key issues limiting its development in some applications. This paper presents a high voltage series-connected silicon carbide (SiC) metal-oxide -semiconductor field effect transistor ( MOSFET s) module which can be served as the main switch in a repetitive high-voltage nanosecond pulse generator. This kind of series-connected MOSFET s module with only single external gate driver requiring very few components is very suitable for compact assembly. By analyzing the working principle, three topologies of series-connected MOSFET s module are proposed. The switching behaviors of the three different topologies with four SiC MOSFET s series-connected are compared experimentally. The variation of switching characteristics of series-connection SiC MOSFET s module with different numbers of devices are investigated. The layout is also optimized to shorten pulse front time and improve output pulse quality. Furthermore, a 10 kV SiC MOSFET s module with a turn- on transition time ∼10 ns is developed. The double pulse test result demonstrates excellent switching performances. Finally, a compact and high-voltage pulse generator composed of three 10 kV SiC MOSFET s module is tailored, with a typical rise time ∼40 ns and peak voltage of ∼30 kV.

A Single Gate Driver Based Solid-State Circuit Breaker Using Series Connected SiC MOSFETs

Abstract: Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfet s), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfet s to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on -state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs.

A Low Gate Turn-OFF Impedance Driver for Suppressing Crosstalk of SiC MOSFET Based on Different Discrete Packages

Abstract: Because of higher switching speed of silicon carbide MOSFET, the crosstalk in a phase-leg configuration will be more serious, which hinders the increase of switching frequency and lowers the reliability of the power electronic equipment. The displacement current of the gate–drain capacitor and the voltage drop on the common-source inductors can induce the crosstalk. In order to suppress the crosstalk, this paper proposes a novel gate driver, in which two additional capacitors are added to create the low turn-off gate impedance. With this proposed driver, the common-source parasitic inductor can be decoupled from the gate loop and the displacement current of the gate–drain capacitor can be bypassed. In addition, the operating principle and the parameters design are also analyzed. Finally, the crosstalk in the non-Kelvin package and the Kelvin package are tested by experiments, the validity of the analysis and the effectiveness for suppression the crosstalk are proved as well.

Achieving Zero Switching Loss in Silicon Carbide MOSFET

Abstract: Due to the unipolar conduction mechanism, the switching loss of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor ( mosfet ) is reduced significantly when compared with silicon insulated gate bipolar transistor (IGBT). This enables the use of SiC mosfet in high-frequency application. However, the switching loss could still thermally limit the upper limit of the switching frequency. Further reduction of switching loss of SiC mosfet , therefore, remains an open challenge for higher frequency applications. Based on the in-depth revelation of device physics of the switching process, accurate switching loss model is established which highlights the dependence of the switching loss on the gate driving condition. With extreme fast gate driving condition, several loss limitations can be established. The minimum turn- on loss is the energy stored in the output capacitance and the minimum turn- off loss can approach zero or the so-called zero turn- off loss (ZTL). Furthermore, zero switching loss (ZSL) is achieved when utilizing zero-voltage switching turn- on and ZTL turn- off condition. With ZSL, the upper limit of the switching frequency is no long thermally limited which is verified by co-package experimental demonstration. We believe the trailblazing concepts of SiC mosfet switching loss will provide guiding principles for device innovation, package optimization, gate driver improvement, and current possible solutions toward higher frequency applications.

Gate–Emitter Pre-threshold Voltage as a Health-Sensitive Parameter for IGBT Chip Failure Monitoring in High-Voltage Multichip IGBT Power Modules

Abstract: This paper proposes a novel health-sensitive parameter, called the gate–emitter pre-threshold voltage V GE(pre-th), for detecting IGBT chip failures in multichip IGBT power modules. The proposed method has been applied in an IGBT gate driver and measures the V GE at a fixed time instant of the V GE transient before the threshold voltage occurs. To validate the proposed method, theoretical analysis and practical results for a 16-chip IGBT power module are presented in the paper. The results show a 500 mV average shift in the measured V GE(pre-th) for each IGBT chip failure.

Active Gate Driver for SiC-MOSFET-Based PV Inverter With Enhanced Operating Range

Abstract: For photovoltaic (PV) inverter applications, the grid code mandates reactive power support to the grid, and the amount of reactive power injection may be limited by the voltage overshoot during the switching transients of a power device. For SiC- mosfet -based PV inverters, this problem is more pronounced since the voltage and current gradient during switching transitions are much higher than a Si-based power converters. During a cloudy day when the inverter has to operate at PV panels open-circuit voltage, it becomes harder to push higher reactive power support to the grid due to the current derating of the SiC-devices at the operating dc bus voltages to keep the device within its safe operating limits with low switching losses at all operating conditions. Slowing down the switching transient could be a remedy but this also increases the converter losses. This paper demonstrates an application of a dynamic gate resistance modulation technique to keep the SiC-device within its safe operating limits while maintaining a low switching loss with minimum voltage and current overshoots. This helps to inject more power to the grid with at higher dc bus voltages without enhancement of the thermal management system. The proposed implementation also works equally well at high junction temperatures (up to $T_j = 150$ °C), which further increases the operating range of the PV inverter.

An Integrated SiC CMOS Gate Driver for Power Module Integration

Abstract: With high-temperature power devices available, the support circuitry required for efficient operation, such as a gate driver, is needed as part of a complete high-temperature solution. The design of an integrated silicon carbide (SiC) gate driver using a 1.2-μm complementary metal–oxide–semiconductor (CMOS) process is presented. Adjustable drive strength is added to facilitate a minimal external component requirement for high-temperature power modules and lays the groundwork for dynamic adjustment of drive strength. The adjustable drive strength feature demonstrates a capability of reducing overshoot and controlling dv / dt dynamically. Measurement of the gate driver was performed driving a power mosfet gate over temperature, exceeding 500 °C. High-speed and high-voltage room temperature evaluation is provided, demonstrating a system capable of high performance over temperature. The driver accomplishes better than 75 ns of rise and fall time driving the Cree CPM3-0900-0065B from room temperature to over 500 °C indicating that it will be ideal for integration into an all-SiC power module where driver, protection circuits, and power devices are fabricated in SiC.

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Abstract: Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and sub-ns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/( $\mu $ mV), which is an $1.7\times $ improvement on the next best reported level shifter for this type of application.

A Comparison Review of the Resonant Gate Driver in the Silicon MOSFET and the GaN Transistor Application

Abstract: The increasing transistor power loss brought by the high switching frequency places a limit to the future high power density converter design. A review of resonant gate drivers is given in this paper to provide a vision for its future application. Various resonant gate driver topologies from the prior-art research is categorized and thoroughly compared in terms of the implementation frequency and the percentage gate driver loss reduction. Moreover, a case study of two representative resonant gate driver topologies is given. The conventional gate drive and two resonant gate drivers are implemented to driver Silicon MOSFETs and Gallium Nitride transistors, respectively. The feasibility and effectiveness of implementing resonant gate drivers in wide-bandgap semiconductor transistors is discussed according to a detailed comparison of loss decomposition.

A Smart IGBT Gate Driver IC With Temperature Compensated Collector Current Sensing

Abstract: Conventional insulated gate bipolar transistor (IGBT) current sensing and protection techniques usually employ discrete sensors, such as lossy shunt resistors, and may involve accessing the high-voltage collector load of the IGBT. This would normally present difficulties for integration. This paper presents an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for local data processing. This IC is prototyped using a TSMC 0.18 μm 40 V BCD Gen-2 process. The collector current sensing technique is based on the unique Miller plateau relationship between the gate current and collector current ( $I_{C}$ and $I_{G}$ ) for a particular gate resistance ( $R_{G}$ ). It allows a cycle-by-cycle measurement of IC during both turn- on and turn- off transients without any extra discrete components. The temperature variation is compensated internally by the on-chip CPU using polynomial curve fitting. This technique only monitors the low-voltage signal at the gate terminal, without the need to handle any high-voltage signal on the collector/load side. Measurements using a double pulse test setup show an accuracy of ±0.5 A over the current ranges of 1–30 A for turn- on and 1–50 A for turn- off from 25 to 75 °C.

An Improved Active Crosstalk Suppression Method for High-Speed SiC MOSFETs

Abstract: Silicon carbide (SiC) power electronic devices feature the advantages of fast switching speed, low conduction loss, and reliable operation in high temperature environment, etc. Due to the differences of parasitic parameters and threshold voltage between SiC mosfet s and Si mosfet s, crosstalk problem is easy to be triggered when SiC mosfet s are applied to bridge topologies. In this paper, the crosstalk effect with different parasitic parameters of SiC mosfet s is firstly analyzed, and then an improved active crosstalk suppression method for high-speed SiC mosfet s is proposed. By using the proposed method, when the crosstalk occurs, the crosstalk voltage will be decreased by reducing the equivalent gate resistance and increasing the equivalent gate-source capacitance in an active way. Consequently, the crosstalk problem can be suppressed without affecting the switching speed. To verify the effectiveness of the proposed method, a prototype of a buck–boost converter is built and the proposed modified gate driver is applied to the half-bridge topology. Comparative experimental study is conducted and the crosstalk voltage is analyzed. The experimental results verify that effective crosstalk suppression is achieved.

System Optimization of a High Power Density Non-Isolated Intermediate Bus Converter for 48 V Server Applications

Abstract: With the power architecture transition from a 12 to 48 V rack in modern data centers, there is an increased interest in improving 48 V power conversion efficiency and power density. In this paper, we will analyze system optimization for a 48–12 V non-isolated, fully regulated, intermediate bus converter (IBC) to maximize efficiency and power density. This includes detailed analyses on the impact of power semiconductor device, gate driver as well as an exhaustive treatise on the choice of the optimal inductor. The final experimental prototype, a fully regulated, digitally controlled, 720 W, five phase, GaN transistor-based 48–12 V buck IBC demonstrates exceptional efficiency and power density, respectively, exceeding 95% and 1000 W/in3.

Medium Voltage (13.8 kV) Transformer-less Grid-Connected DC/AC Converter Design and Demonstration Using 10 kV SiC MOSFETs

Abstract: Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, challenges still exist on the components design considering HV insulation and noise immunity requirements in the MV SiC based power converter. A 5-level MMC based transformer-less grid-connected dc/ac converter is developed for 13.8 kV medium voltage grid using 10 kV SiC MOSFETs. The key components, including gate driver with high dv/dt immunity and fast reliable protection, isolated power supply with low parasitic capacitance, voltage/current sensors with high noise immunity, and passives following related insulation standard are provided. A 25 kV dc-link phase-leg is demonstrated, and the experimental results are presented.

Characterization and Performance Evaluation of the State-of-the-Art 3.3 kV 30 A Full-SiC MOSFETs

Abstract: With their intrinsic superiorities such as high breakdown electric field and high thermal conductivity, the silicon carbide (SiC) mosfet s are replacing traditional Si insulated gate bipolar transistor (IGBTs) in power electronics applications. However, at higher voltages, SiC mosfet s are at early stages of development and are not commercialized yet. This paper presents thorough static and dynamic performance characterization of 3.3 kV and 30 A discrete full-SiC mosfet s. The devices under test are noncommercialized samples from Sumitomo Electric Industries, Japan. A complete static characterization is performed on the devices under test from 25 up to 150 °C to reveal their characteristics and their dependency on temperature. Also, for dynamic tests, a double-pulse tester with a high-performance gate driver circuit is designed, and tests are performed at 25, 100, and 150 °C. Key characteristics such as on -resistance and switching losses are compared to those of a Si IGBT with similar voltage and current rating in order to assess advantages of SiC mosfet s over existing Si semiconductors. Following static and dynamic characterizations, the performance of the devices is evaluated in a boost converter topology, and the results are compared to that of Si IGBTs. The evaluation results reveal significant superiority for SiC mosfet s in terms of efficiency, maximum possible switching frequency, and system power density.

Optimization Platform to Find a Switching Pattern of Digital Active Gate Drive for Reducing Both Switching Loss and Surge Voltage

Abstract: A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern.

Reduction of EMI Noise Due to Nonideal Interleaving in a 100 kW SiC PV Converter

Abstract: A Grid-tied inverter utilizing wide bandgap devices can achieve higher switching frequency resulting in a power filter with reduced size and weight. However, the increased switching frequency may lead to more switching harmonics entering the electromagnetic interference (EMI) frequency range, which will increase the size of EMI filter. Interleaving paralleled converters can cancel some of the switching harmonics and reduce the size of EMI filter. However, nonideal interleaving will deteriorate the harmonic canceling effect. In this research, the nonideal effects are found to be from the small mismatch of the pulsewidth of the interleaving legs and the mismatch of the impedance between the interleaving legs. A modulation method is proposed to completely eliminate the pulsewidth mismatch. Compared with other solutions, the proposed method does not require the information of filter parameters, neither gate driver synchronization, and nor a special function block of the digital controller. The proposed modulation was implemented on a 150 MHz digital signal processor and a 100 MHz field-programmable gate array, and was experimentally verified on a 100 kW parallel coupled SiC PV inverter prototype.

Ripple-Free Boost-Mode Power Supply Using Photonic Power Conversion

Abstract: Photonic power converters (PPCs) are a class of photovoltaic devices designed for efficient conversion of monochromatic (laser or LED) light to electricity. These devices are composed of multiple p-n junction diodes arranged in a tandem configuration and connected in series. They have reached high energy conversion efficiencies (70%) and areal power densities of 100 W/cm $^2$ . When these devices are illuminated with a high-efficiency diode laser, they can provide isolated dc–dc conversion from the laser voltage ( $^{3}$ , compared with 1.5 W/cm $^{3}$ for the reference. Relative to switch-mode power conversion, the photonic technology has lower efficiency and lower power density, but superior isolation and rejection of ripple and EMI. Both technologies are highly scalable. For the second application, the same unit is applied to power a 650-V SiC mosfet gate driver requiring high galvanic isolation, demonstrating a 20 dB reduction in conducted-current EMI from the power circuit into the low-voltage control systems.

Design of Active SiC MOSFET Gate Driver for Crosstalk Suppression Considering Impedance Coordination between Gate Loop and Power Loop

Abstract: In a phase leg configuration of SiC MOSFETs, the crosstalk threatens the reliable operation of the devices and introduces additional loss. State-of-the-art methods suppressing the crosstalk fails to consider the influence of the gate loop impedance. This paper points out that the gate loop impedance should be carefully designed in terms of the crosstalk elimination, especially for SiC MOSFET with fast switching speed and low threshold voltage. Firstly, an impedance model considering the parasitics of the gate loop is proposed. Then it is pointed out that the crosstalk voltage induced across the impedance of the gate source of the SiC MOSFET is related to the oscillation frequency of the drain source ring voltage, which is decided by the parasitics of the power loop. To effectively eliminate the crosstalk voltage, the gate loop impedance and power loop impedance should be designed coordinately. Finally, a parallel capacitor of the gate source terminal of SiC MOSFET is added during the turn off period and with proposal capacitance selection, the crosstalk voltage is effectively reduced. The proposed analysis and method are experimentally verified through a double pulse test platform.

Three-Phase Single-Stage-Isolated Cuk-Based PFC Converter

Abstract: In this paper, analysis and design of a three-phase-isolated Cuk-based power factor correction (PFC) converter have been proposed. The proposed converter is operated in discontinuous output inductor current mode to achieve PFC at ac input. This avoids the inner current control loop which further eliminates the sensing of current. This makes the system more reliable and robust. The converter requires only one simple voltage control loop for output voltage regulation, and all the power switches are driven by the same gate signal which simplifies the gate driver circuit. The detailed operation of the converter and design calculations are presented. And also a small-signal model of the converter by using current injected equivalent circuit approach is presented to aid the controller design. The experimental results from a 2-kW laboratory prototype with 208-V line-to-line input voltage, 400-V output voltage are presented to confirm the operation of the proposed converter. An input power factor of 0.999, an input current total harmonic distortion of as low as 4.06%, and a high conversion efficiency of 95.1% are achieved from laboratory prototype.

On the Techniques to Utilize SiC Power Devices in High- and Very High-Frequency Power Converters

Abstract: In this paper, we explore the challenges of implementing resonant converters using silicon carbide (SiC) power devices at high frequency: namely, the issue of high parasitic inductance packages and the ability to drive and enhance the mosfet at these frequencies. Although power circuit designers have many alternative device technologies to choose from, such as silicon and gallium nitride materials, SiC devices have several advantageous attributes especially in high power applications. As a solution, we study the device performance and parasitics of SiC mosfet s in different packaging schemes. We further offer a solution to the challenges of driving SiC devices by demonstrating a multiresonant gate driver and use this scheme to drive an SiC mosfet at 30 MHz and a SiC JFET at 13.56 MHz in a class-E inverter, achieving 85.7 $\%$ drain efficiency for the mosfet and 93.8 $\%$ for the JFET.

A Novel High-Gain Switched-Capacitor Based 11-Level Inverter Topology

Abstract: This paper proposes a new 11-level high step-up switched-capacitor based inverter topology. The suggested topology uses only one DC source and can produce a gain of 5. Also it can produce high ratios of steps per switches, gate driver circuits and DC sources, which leads to less devices, less volume, weight and expense. The Total Harmonic Distortion (THD) of produced voltage is low. So, the size of output filter can be reduced. Also, the suggested structure can be well applied on supplying low power factor $R-L$ loads. Natural voltage balancing of capacitors is another main merit of suggested structure that results in simple and easy control strategy. The suggested configuration has been introduced and its operational modes have been explained. Then it has been compared with novel similar topologies and simulated in MATLAB-SIMULINK. The comparison and simulation results confirm the appropriate features and proper operation of suggested configuration.

Stray Impedance Measurement and Improvement of High-Power IGCT Gate Driver Units

Abstract: Turn-off capability of integrated gate-commutated thyristor is highly dependent on the commutation capability of its gate driver unit (GDU). To enhance it, stray impedance is the crucial limitation, which has not been obtained accurately before. Thus, in this paper, acquisition method of impedance based on experimental measurements was carefully analyzed, including electrolytic and ceramic capacitors, mosfets , printed circuit board, and GCT housing. And each part of stray impedance was obtained based on a series of experiments with 6-inch GCTs and two types of conventional GDUs. To further enhance commutation speed, an improved GDU was developed, reducing the total stray inductance from 0.395 to 0.037 nH, stray resistance from 0.444 to 0.227 mΩ. An extremely high current of 12.5 kA was successfully turned off, which is the maximum turn-off current level so far. Besides, the maximum commutation capability was tested as over 17 kA. Consequently, no further optimization of GDU is necessary. However, there was still about 1.0 nH existing inside the GCT housing we used. A novel housing with lower stray inductance is expected for higher commutation speed in the future.

Monolithic integration design of GaN-based power chip including gate driver for high-temperature DC-DC converters

Abstract: Power integration is essential for the fully utilization of advanced GaN devices in power conversion applications due to the reduced parasitic inductance, low on-state resistance, and high-temperature operation. This paper presents a GaN-based monolithic integration design with optimized gate drivers for high-temperature DC?DC converters. Four different gate drivers are experimentally evaluated for integration with boost converters based on enhancement (E)-mode AlGaN/GaN metal?insulator?semiconductor heterojunction-field-effect-transistors (MIS-HFETs). The optimized gate driver, consisting of DCFL (Direct-Coupled FET Logic) inverters and a buffer amplifier, can operate over a wide temperature range (from 25??C to 250??C). Furthermore, a 100?kHz, 5?V/11?V (V IN/V OUT) boost converter prototype with the proposed monolithic integration design was built and found to operate successfully under high temperatures (HTs) up to 250??C. These results validate the advantages of GaN-based monolithic integration techniques in achieving HT, high power density, and high efficiency power converters.