Showing papers on "Gate oxide published in 2021"

A New Complete Condition Monitoring Method for SiC Power MOSFETs

Abstract: This article proposes a new complete condition monitoring method which can independently monitor both the threshold voltage drift and the packaging degradation accurately by monitoring only the reverse body diode voltage drop at different gate bias levels. The SiC MOSFETs are aged through an accelerated aging method and the corresponding changes in electrical parameters are periodically measured to assess their correlation with the state of the device's health. It has been revealed that the on -state resistance reveals the combination of gate oxide and package-related degradation while the threshold voltage mainly depicts gate oxide-related issues. Unlike these two parameters, the body diode voltage drop is found to independently indicate the state of device health both for package and gate oxide. This is caused by a unique secondary conduction mode of SiC MOSFETs in third-quadrant operation which is clearly disclosed with transition boundaries by a proposed body diode transfer characterization curve. In order to have a detailed condition information of the device with a simple circuit, monitoring the reverse body diode voltage drop at 0 and $-$ 5 V gate bias is proposed. The proposed condition monitoring method is implemented on a gate drive circuit and experimental results are given for two artificially degraded devices. The experimental results confirm that the proposed method can independently monitor both the gate oxide and packaging degradations accurately by monitoring a single precursor parameter. The proposed method can be integrated into the gate driver or converter itself to monitor SiC devices.

Sensitivity Analysis of a Novel Negative Capacitance FinFET for Label-Free Biosensing

Abstract: We propose and analyze a dielectric modulated (DM) negative capacitance (NC) fin-field effect transistor (FinFET) based biosensor for efficient and label-free detection of biomolecular entities. For the first time, the NC effect on bio-sensing owing to the presence of a dielectric-ferroelectric gate oxide stack is investigated. First, capability of the NC-FinFET is compared with the baseline FinFET as percentage variation in electrical parameters. Also, the sensing capability of the proposed device is examined with a wide variety of biomolecules with varying dielectric constants. Inclusion of the NC effect in the biosensor exhibits very high sensitivity in terms of the electrical figures of merit (FoMs) such as threshold voltage, $I_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ -ratio, output conductance, and intrinsic gain with rapid response because of the steep subthreshold value. The use of raised source drain (RSD) architecture allows more cavity space to the biomolecules and, hence, increases the sensitivity and selectivity of the biosensor. All the device simulations are performed in a 3-D Sentaurus TCAD environment using well-calibrated structure. To establish a benchmark, the sensitivity of the proposed biosensor is also compared with the published literature in order to determine its effectiveness. The results of this study can establish NC-FinFET as a viable candidate for label-free DM biosensor applications.

Effect of Curie Temperature on Ferroelectric Tunnel FET and Its RF/Analog Performance

Abstract: In this article, a numerical simulation study for the ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET) has been presented. The performance of the device is analyzed following Landau’s theory and its behavior in the temperature range of 200–300 K. A minimum subthreshold swing and maximum transconductance is obtained around the Curie temperature ( ${T}_{C}$ ) of 580 ± 10 K for the simulated device. The simulation result is supported by the simple analytical model. The temperature sensitivity analysis is studied on different analog and RF figure of merits for Ferro-TFET. In this study, the Ferro-TFET shows the remarkable result in reducing the detrimental effect of mobility degradation at high gate voltage and performance degradation at high temperatures as compared to conventional TFETs and MOSFET. Therefore, at Curie temperature, the operation of the Ferro-TFET shows the remarkable results for analog and RF applications.

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

Abstract: In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 + HfO2) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1) with workfunction (ϕ1), Control gate (M2) with workfunction (ϕ2) and auxiliary gate (M3) with workfunction (ϕ3). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (ϕ1 = ϕ2 = ϕ3). Simulation results shows that the workfunction combination (ϕ1 = ϕ3 < ϕ2) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47× 10− 4A/μm), ION/IOFF (3.14× 1012), point subthreshold slope (15.7mV/decade), transconductance (1.02× 10− 3S), cut-off frequency (1.93× 1011Hz) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications.

High-k 2D Sb2O3 Made Using a Substrate-Independent and Low-Temperature Liquid-Metal-Based Process.

Abstract: High dielectric constant (high-k) ultrathin films are required as insulating gate materials. The well-known high-k dielectrics, including HfO2, ZrO2, and SrTiO3, feature three-dimensional lattice structures and are thus not easily obtained in the form of distinct ultrathin sheets. Therefore, their deposition as ultrathin layers still imposes challenges for electronic industries. Consequently, new high-k nanomaterials with k in the range of 40 to 100 and a band gap exceeding 4 eV are highly sought after. Antimony oxide nanosheets appear as a potential candidate that could fulfill these characteristics. Here, we report on the stoichiometric cubic polymorph of 2D antimony oxide (Sb2O3) as an ideal high-k dielectric sheet that can be synthesized via a low-temperature, substrate-independent, and silicon-industry-compatible liquid metal synthesis technique. A bismuth-antimony alloy was produced during the growth process. Preferential oxidation caused the surface of the melt to be dominated by α-Sb2O3. This ultrathin α-Sb2O3 was then deposited onto desired surfaces via a liquid metal print transfer. A tunable sheet thickness between ∼1.5 and ∼3 nm was achieved, while the lateral dimensions were within the millimeter range. The obtained α-Sb2O3 exhibited high crystallinity and a wide band gap of ∼4.4 eV. The relative permittivity assessment revealed a maximum k of 84, while a breakdown electric field of ∼10 MV/cm was observed. The isolated 2D α-Sb2O3 nanosheets were utilized in top-gated field-effect transistors that featured low leakage currents, highlighting that the obtained material is a promising gate oxide for conventional and van der Waals heterostructure-based electronics.

High Output Power Density of 2DHG Diamond MOSFETs With Thick ALD-Al 2 O 3

Abstract: This article reports on the high operation voltage large-signal performance of two-dimensional hole gas diamond metal–oxide semiconductor field-effect transistors (MOSFETs) with thick atomic-layer-deposition (ALD)-Al2O3 formed on high purity polycrystalline diamond with a (110) preferential orientation. MOSFETs with a 1- $\mu \text{m}$ gate-length having a gate oxide layer of 200-nm-thick Al2O3, formed by ALD and asymmetric structures, to withstand high-voltage operations. The large-signal performances were evaluated at a quiescent drain voltage of greater than −60 V for the first time in diamond field-effect transistor (FET). As a result, an output power density of 2.5 W/mm under class-A operation at 1 GHz, which is higher than that of diamond FETs fabricated by a self-aligned gate process, was obtained. Moreover, an output power density of 1.5 W/mm was exhibited by the MOSFET when biased at a quiescent drain voltage of −40 V under class-AB operation at 3.6 GHz using an active load-pull system. This is the highest recorded value for diamond FETs at a frequency greater than 2 GHz, owing to the high-voltage operation. These results indicate that diamond p-FETs under high-voltage operations are the most suitable for high-power amplifiers with complementary circuits.

Investigation of Gate Leakage Current Behavior for Commercial 1.2 kV 4H-SiC Power MOSFETs

Abstract: The commercialization of silicon carbide (SiC) power metal-oxide-semiconductor field-effect-transistors (MOSFETs) has expanded during the last decade. The gate oxide reliability is the primary issue for SiC power MOSFETs since it determines the device's operational lifetime. In this work, we investigate the gate leakage currents under different gate voltages on commercial 1.2 kV SiC power MOSFETs. The impact ionization and/or anode hole injection (AHI) triggered by high oxide electric fields results in hole trapping that enhances the gate leakage current and reduces device's threshold voltage. The electron injection and trapping due to Fowler-Nordheim (F - N) tunneling tend to reduce the gate leakage current and increases threshold voltage. Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are also conducted on the commercial MOSFETs. The results on gate leakage current suggest that the change of the field acceleration factor is due to enhanced gate current/hole trapping under high gate oxide fields. Therefore, it is suggested that TDDB measurements should be conducted under low gate voltages to avoid overestimation of lifetime under normal operating gate voltage.

Investigation of interface trap charges and temperature variation in heterostacked-TFET

Abstract: This paper analyzes the reliability issues of the Heterostacked-TFET (HS-TFET) in detail. The investigation of the device reliability is carried out by examining the effect of interface trap charges (ITCs) and the temperature affectability of the HS-TFET on various analog parameters and RF FOMs. The analysis is performed at different interface trap charge densities and polarities. The presence of interface traps at the stackedsource/channel junction and the oxide/silicon interface alters the performance of the device significantly. A positive trap charge density of 3 × 1013 cm−2 degrades the current switching ratio tremendously from an order of 1010–104. The off-state current of the device deteriorates excessively at high temperatures. However, the results establish that the HS-TFET is insusceptible to the acceptor interface trap charge as compared to the donor interface trap charge for temperature variation. A high-k gate dielectric of Aluminum oxide (Al2O3) is considered and compared with Hafnium oxide (HfO2) and it is found that Al2O3 gate oxide has a better immunity to the ITC variation.

Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance

Abstract: In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this small scale of gate length. Both oxide widths of high K-material HfO2 have their own individual benefits, due to high gate controllability as compared to conventional FinFETs having SiO2 as a gate oxide. The device works best with Tox = 1 nm in terms of power amplification. When tested with this width of gate oxide, we end up with increase of 59.18%, 7.22% and 12.11 times at corresponding peak values of Unilateral power gain (Gu), IP3 and fmax. This actually evident the enhanced performance of TF-FinFET for A.C applications at this high range of frequency of the input signal. When device tested at Tox = 1 nm, we end up with the increase of 45%, 21.45%, 16% and decrease of 65% at the corresponding peak values of Intrinsic delay (ti), Transconductance (gm), Drain current (ID) and OFF-state current (IOFF). These results of simulation also showed the compatibility of TF-FinFET in terms of high-performance analog application. After these analyses, we can expect a strong potential for wide variety of applications to high-speed System on chip from this device.

A Low Power Single Gate L-shaped TFET for High Frequency Application

Abstract: In this manuscript, we have optimize the single gate L-shaped Tunnel field effect transistor (SG-L-TFET) for low power application. In this regard, the simulated SG-L-TFET comprises high ON-current (I ON ) with low OFF-current (I OFF ) and very low sub-threshold swing value (SS) than Conventional dual gate TFETs (DG-TFETs). The high I ON is achieved in the SG-L-TFET because of the increased cross-sectional area of band-to-band tunneling (BTBT) junction. In this device structure, BTBT tunneling junction is perpendicular to channel direction which one is differ from the conventional TFET tunneling barrier length (L T ). It is more scaleble than other vertical-BTBT-based TFET designs and provides higher I ON than a conventional planar TFET with the same gate overdrive voltage (V ov ) of 0.8 V. In this work, analysis has been carried out for the optimization of drain length (L D ), source length (L S ), dielectric material variation for gate oxide and lower band gap material for source region. Simulation results have confirmed the superiority of SGL-TFETs over the conventional TFETs. In addition, the outcome of device parameters variation on the device functioning has been investigated for the comprehensible validation of its optimization.

Analytical and Compact Modeling Analysis of a SiGe Hetero-Material Vertical L-Shaped TFET

Abstract: This paper deals with the development of a novel 2-D analytical modeling of heterojunction vertical L-shaped tunnel FET for characterisation of surface potential and drain current. The compact analysis includes the properties of dual modulation effect with the numerous efforts to predict the characteristics of current and to discuss the method of device improvement. The dual modulation effect is used to regulate the biasing voltage at both the junction of source and drain of surface potential to determine the tunneling width. A 2-D Poisson equation is solved for the proposed model by using parabolic approximation method with constant electric field which are used to determine the effect of SiGe mole-fraction, gate-drain biasing potential, dielectric constant of gate oxide, drain doping concentration, metal gate work-function and different binary compound material on the device surface potential. Most importantly, a new channel surface potential expression is derived that can forecast the effect of drain and gate biasing. The derived model results are compared with those of simulated results in order to evaluate the validity of electrical parameter model.

Design and Investigation of Dielectrically Modulated Dual-Material Gate-Oxide-Stack Double-Gate TFET for Label-Free Detection of Biomolecules

Abstract: This article investigates the applicability of dual-material gate-oxide-stack double-gate tunnel field effect transistor (DMGOSDG-TFET) as a biosensing element with the ability to assess the health parameters and disease onset. For this, employment of gate work-function engineering along with the gate-oxide-stack approach and asymmetrical doping at ${p}^{+}$ source and ${n}^{+}$ drain region are introduced for the first time to implement DMGOSDG-TFET-based biosensor. Also, a nanogap cavity is created by etching a portion of gate dielectric material toward the source end for the accomplishment of biomolecules conjugation in the proposed device. The main focus of this article is to estimate the underlying device sensitivity in the presence of different charged as well as neutral biomolecules. To explore such effects, different dielectric constants and negative charge densities of the biomolecules are considered independently in the nanogap cavity. Next, the sensing performance of the presented device is analyzed in terms of switching-ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), transconductance-to-current ratio ( ${g}_{m}/{I}_{ds}$ ), and average subthreshold-swing. A deep investigation of device performance is also performed with different fillings of the nanogap cavity and step-profiles arising out from the steric hindrance. The device sensitivity is analyzed for different cavity lengths and cavity thicknesses for the best outcomes. In addition, a comparative sensitivity analysis of DMGOSDG-TFET with single-material gate-oxide-stack double-gate tunnel field effect transistor (SMGOSDG-TFET) and metal–oxide–semiconductor field effect transistor (MOSFET)-based biosensor is also presented in this work. The device implementation and all the simulations are carried out using technology computer-aided design (TCAD) tool. All of the sensitivity-assessments disclose that DMGOSDG-TFET can be a good candidate for biosensing applications.

Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal & Investigation For Optimized Device Performance

Abstract: This paper reports an unique approach to suppress ambipolarity and enhance drive current in tunnel field effect transistor (TFET) by incorporating vertically extending drain in double gate Si1−xGex source TFET. This structure has dual source extending laterally on both sides of the channel with vertically extended drain over the T-shaped channel (VD-DG-Si1−xGexS-TFET). Our study is based on calibrated exhaustive 2-D TCAD simulations. It advocates that the device performance is not only retained but significantly enhanced even by deploying only double gate instead of quadruple gate with Si1−xGex sources. Further the drive current can be significantly increased by optimizing the mole fraction (x) in Si1−xGex source. Our study reveals that the average subthreshold slope (SSavg) is 23.98 m V/dec (point SS (SSpoint) is 12.7 m V/dec with sub-60 m V/dec point SS for 107 orders of current change), drive current (ION) is 2.73× 10− 4 A/um and 46% improvement in transconductance as compared to the earlier reported drain engineered quardruple gate TFET. Further the device sensitivity analysis with respect to gate oxide dielectric constant, gate metal work-function, temperature and germanium mole fraction variation is also analyzed here. Moreover, in terms of device analog behaviour, the cut off frequency (ft) is reported as 38.93 GHz and 140% increment in gain bandwidth product (GWB) as compared to its quardruple gate alternative. This study proves the potentials of considered device structure as a promising candidate for ultra low power analog/RF and digital logic applications.

Analytical Model of Dielectric Modulated Trench Double Gate Junctionless FET for Biosensing Applications

Abstract: A 2-D analytical model of a dielectric modulated trench double gate junctionless FET (DM-TDGJLFET) is developed for label-free detection of biomolecules The channel potential is obtained by solving the 2-D Poisson’s equation using the parabolic approximation with appropriate boundary conditions The drain current and threshold voltage are obtained from the minimum channel potential The proposed DM-TDGJLFET structure has two gates which are vertically placed in separate trenches The two cavities for biomolecules immobilization are carved in the gate oxide region The DM-TDGJLFET has been studied for threshold voltage sensitivity of neutral as well as charged biomolecules For neutral biomolecules, the shift in threshold voltage is obtained as $745 {mV}$ for change in dielectric constant ( ${k}$ ) from 1 to 12 The DM-TDGJLFET performance is also evaluated using commercially available $ {ATLAS}^{ {TM}}$ device simulator The model results show good agreement with simulated data

Investigation on Degradation of SiC MOSFET Under Accelerated Stress in a PFC Converter

Abstract: The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this article, we report the long-term degradation phenomenon of several types of SiC MOSFETs in an actual 2-kW power factor correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional dc power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in a PFC converter. Online monitoring results show that the ON-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in ON-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain–source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation, and $C$ – $V$ measurement indicate that the main degradation mechanism is hot holes accumulation within the gate oxide above the JFET region and channel region due to high electric field stress.

Investigation on Short-Circuit Characterization and Optimization of 3.3-kV SiC MOSFETs

Abstract: The short-circuit (SC) ruggedness of 3.3-kV silicon carbide (SiC) MOSFETs is of great importance for traction applications. In this article, the SC characterization and failure mechanism of 3.3-kV planar-gate SiC MOSFETs are systematically studied by experiments and simulations. The measured SC withstanding time (SCWT) of 3.3-kV SiC MOSFETs is about $17~\mu \text{s}$ , and the SC energy density is 15.5 J/cm2. Research demonstrates that the current clamping phenomenon is attributed to the high density of interface traps ( ${D}_{\text {it}}$ ) in the gate oxide of 3.3-kV SiC MOSFETs. Furthermore, the positive temperature feedback mechanism and the triggering of parasitic n-p-n transistor are proved to cause the SC failure. At last, three optimized cell structures are proposed for improving the SC capability of 3.3-kV SiC MOSFETs, where the optimal SCWT is enhanced by 23% without degrading the forward conduction capability.

Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

Abstract: This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO 2 -Based Ferroelectric Field Effect Transistor

Abstract: The endurance of the HfO2-based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (Tramp), which is the time to reach the PG/ER voltage, and the hold time (Thold), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 104 by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long Tramp but short Thold are desirable to suppress the interface trap generation in FeFET. The relation between Tramp, Thold and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).

A design of nanoscale double-gate FET based ring oscillator with improved oscillation frequency using device engineering

Abstract: In this paper, the performance of inverter and ring oscillator circuits based on the nanoscale double-gate (DG) FET is improved by using device engineering approaches. The modification of the parameters affecting the intrinsic delay time of the DGFET, such as on-current and the total gate capacitance can be improved the oscillation frequency of the ring oscillator. Accordingly, the effects of gate oxide thickness ( t ox ) and body thickness ( t body ) on the electrical characteristics of the device and circuit-level have been investigated so that we could provide a design of ring oscillator with improved oscillation frequency. Moreover, the enhanced source doping concentration and graded-channel (GC) techniques have been applied and analyzed at the device-level to ameliorate the oscillation frequency of the ring oscillator. Finally, we have presented the graded-channel (GC) strategy with two types of high-low (HL) and low-high (LH). The extracted results illustrate that the total gate capacitance of the LH-GC-DGFET is improved significantly compared to the HL-GC-DGFET. Consequently, the efficient design of the ring oscillator based on LH-GC-DGFET with superior oscillation frequency is proposed. The TCAD mixed-mode simulation has been used for simulating the circuits.

Deterministic Shallow Dopant Implantation in Silicon with Detection Confidence Upper-Bound to 99.85% by Ion-Solid Interactions

Abstract: Silicon chips containing arrays of single dopant atoms could be the material of choice for both classical and quantum devices that exploit single donor spins. For example, group-V-donors implanted in isotopically purified 28 Si crystals are attractive for large-scale quantum computers. Useful attributes include long nuclear and electron spin lifetimes of 31 P, hyperfine clock transitions in 209 Bi or electrically controllable 123 Sb nuclear spins. Promising architectures require the ability to fabricate arrays of individual near-surface dopant atoms with high yield. Here we employ an on-chip detector electrode system with 70 eV r.m.s. noise (∼ 20 electrons) to demonstrate near room temperature implantation of single 14 keV 31 P+ ions. The physics model for the ion-solid interaction shows an unprecedented upper-bound single ion detection confidence of 99.85±0.02% for near-surface implants. As a result, the practical controlled silicon doping yield is limited by materials engineering factors including surface gate oxides in which detected ions may stop. For a device with 6 nm gate oxide and 14 keV 31 P+ implants we demonstrate a yield limit of 98.1%. Thinner gate oxides allow this limit to converge to the upper-bound. Deterministic single ion implantation can therefore be a viable materials engineering strategy for scalable dopant architectures in silicon devices. This article is protected by copyright. All rights reserved.

Interface engineering of gate dielectrics with multifunctional self-assembled monolayers in copper phthalocyanine based organic field-effect transistors

Abstract: To enhance the performance of organic field-effect transistors (OFETs) not only properties of gate oxide, active organic layer and source and drain needs to be improved but it is essential to engineer the different interfaces in OFETs. In this aspect, the gate oxide/organic semiconductor and electrode/organic semiconductor interfaces are engineered by various functional groups to obtain high performance OFETs. CuPc-based FETs were fabricated by surface treatment with various self-assembled monolayers (SAMs); octadecyltrichlorosilane(OTS), hexamethyldisilazane (HMDS) and pentaflurothiophenol (PFBT), at an interface between gate oxide or gate dielectric layer and active organic layer. The influence of SAMs on the device performance was examined in the present study. Low-voltage operating CuPc-based OFETs with high field effect mobility were fabricated in current work. Significant development in the device parameters, especially the field effect mobility was observed for HMDS treated CuPc-FET as compared to the OTS and PFBT treated CuPc-FET. The OFETs with the SAM-treatments exhibit the field effect mobility was 5.6 × 10-2cm2 V−1 s−1 (OTS) to 1.369 cm2 V−1 s−1 (PFBT-treated) and 1.537 cm2 V-1s−1 (HMDS-treated).The improved performance of the OFET were related to the improve crystallinity with larger grain size of the organic semiconductor with reduced trap densities and improved contact resistance between the metal electrode and organic semiconductor due to the introduction of monolayer at the interface.

An Improved Analytical Modeling and Simulation of Gate Stacked Linearly Graded Work Function Vertical TFET

Abstract: In this paper, a 2D analytical potential model for n + SiGe Gate stacked linearly graded work function Vertical TFET (n + SiGe GS-LGW-VTFET) is developed with incorporating the effect of source and drain depletion region towards the channel. The proposed novel structure is developed from linearly graded for equalizing disruption of the work function having symmetric potential distribution effect on the device channel, which noticeably improve the device performance by reducing the short channel effect. The Poisson equation is solved in terms of channel surface potential and electric field using the parabolic approximation approach. This model also used some accurate analysis by employing the SiO2 and HfO2 with gate stacking method in order to increase the better gate control over the channel length. This model can initially forecast with the effect of gate-source voltage (Vgs) and drain-source voltage (Vds) thereafter gate oxide thickness, linearly graded work function, and SiGe mole fraction. The electric field is derived using the surface potential model, and thereafter, in order to extract the drain current characteristics, our suggested model accounts for the variables of the Kane model by integrating the band-to-band tunneling generation rate over the tunneling region. The proposed model efficiency has been confirmed by the drive characteristics of our model are in coincides nicely with that of simulation results.

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Abstract: This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO2 and HfxTi1-xO2) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10−14 to 10−17 and ION/IOFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and ION/IOFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.

Verification of Single-Pulse Avalanche Failure Mechanism for Double-Trench SiC Power MOSFETs

Abstract: The failure mechanism of double-trench silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) under single-pulse avalanche stress is verified. Instead of the widely reported burning out failure mechanism for planar-gate devices, double-trench SiC power MOSFETs suffer from a totally different failure mechanism, as they can only endure a much lower maximum single-pulse avalanche energy ( $E_{\mathrm{ as}}$ ). It is found that during the avalanche process, obvious gate leakage current ( $I_{g}$ ) appears, which is resulted from the high impact ionization rate and high electric field along the gate trench bottom oxide interface, especially the trench corners. The $I_{g}$ continuously grows along with the increase in the peak load current ( $I_{\mathrm{ peak}}$ ), eventually leading to the breakdown of the trench bottom gate oxide under avalanche status. By increasing the value of gate resistor ( $R_{g}$ ), the $I_{g}$ raises the gate–source voltage ( $V_{\mathrm{ gs}}$ ) during the avalanche process, forcing the channel region in an inversion state. Part of the avalanche current is then diverted into the forward conductive current, changing the failure mode from breakdown of the gate oxide to burning out of the entire device. Moreover, the influence of different avalanche stress conditions, including the di / dt and the ambient temperature ( $T_{a}$ ), on the single-pulse avalanche endurance capability of double-trench SiC power MOSFETs is investigated. All the samples express a similar failure phenomenon. The higher the di / dt is, the shorter the avalanche time the device can endure. This is because the higher $I_{\mathrm {peak}}$ results in a higher $I_{g}$ during the avalanche process, leading to early failure of the gate oxide. However, the $T_{a}$ rarely influences the $E_{\mathrm{ as}}$ of the device, indicating that the single-pulse avalanche-induced failure of double-trench SiC power MOSFETs has little business with the melting of the lattice or package, demonstrating the correctness of the failure mechanism proposed in this article.

A Novel 4H-SiC Trench MOSFET Integrated With Mesa-Sidewall SBD

Abstract: SiC MOSFET integrated with Schottky barrier diode (SBD) can handle the reverse current during switching operation and reduce the package cost. However, the integrated SBD weakens the high-voltage-withstanding capability of the SiC MOSFET. In this article, a novel 4H-SiC trench MOSFET integrated with mesa-sidewall SBD (TMS-SBD) is proposed and studied with the 2-D simulation. Compared with the trench MOSFET integrated with the SBD locating on the mesa (TM-SBD), the TMS-SBD shows a larger breakdown voltage (BV), a lower electric field in the gate oxide, and a better tradeoff between BV and specific ON-resistance. The TMS-SBD also shows the same current capability as that of the TM-SBD. Due to the removal of one sidewall overlap between the gate electrode and drain electrode, the reverse capacitance of TMS-SBD is lower than that of the TM-SBD. In double-pulse test simulation, the turn-on loss and turn-off loss of the TMS-SBD reduce by 30% and 56% than those of the TM-SBD, respectively. Therefore, the TMS-SBD is a more attractive device in high-voltage, high-reliability, and low-switching-loss applications.

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Abstract: In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

High-Performance and Radiation-Hardened Solution-Processed ZrLaO Gate Dielectrics for Large-Area Applications.

Abstract: Radiation hardness is important for electronics operating in harsh radiation environments such as outer space and nuclear energy industries. In this work, radiation-hardened solution-processed ZrLaO thin films are demonstrated. The radiation effects on solution-processed ZrLaO thin films and InOx/ZrLaO thin-film transistors (TFTs) were systemically investigated. The Zr0.9La0.1Oy thin films demonstrated excellent radiation hardness with negligible roughness, composition, electrical property, and bias-stress stability degradation after radiation exposure. The metal-oxide-semiconductor capacitors (MOSCAPs) based on Zr0.9La0.1Oy gate dielectrics exhibited an ultralow flat band-voltage (VFB) sensitivity of 0.11 mV/krad and 0.19 mV/krad under low dose and high dose gamma irradiation conditions, respectively. The low dose condition had a 103 krad (SiO2) total dose and a 0.12 rad/s low dose rate, whereas the high dose condition had a 580 krad total dose and a 278 rad/s high dose rate. Furthermore, InOx/Zr0.9La0.1Oy thin-film transistors (TFTs) exhibited a large Ion/Ioff of 2 × 106, a small subthreshold swing (SS) of 0.11 V/dec, a small interface trap density (Dit) of 1 × 1012 cm-2, and a 0.16 V threshold shift (ΔVTH) under 3600 s positive bias-stress (PBS). InOx/Zr0.9La0.1Oy TFT-based resistor-loaded inverters demonstrated complete swing behavior, a static output gain of 13.3 under 4 V VDD, and an ∼9% radiation-induced degradation. Through separate investigation of the radiation-induced degradation on the semiconductor layer and dielectric layer of TFTs, it was found that radiation exposure mainly generated oxygen vacancies (Vo) and increased electron concentration among gate oxide. Nevertheless, the radiation-induced TFT instability was mainly related to the semiconductor layer degradation, which could be possibly suppressed by back-channel passivation. The demonstrated results indicate that solution-processed ZrLaO is a high-potential candidate for large-area electronics and circuits applied in harsh radiation environments. In addition, the detailed investigation of radiation-induced degradation on solution-processed high-k dielectrics in this work provided clear inspiration for developing novel flexible rad-hard dielectrics.

Investigation of N + SiGe Gate Stacked V-TFET Based on Dopingless Charge Plasma for Gas Sensing Application

Abstract: In this paper, a novel n + SiGe pocket layer gate stacked VTFET doping less charge plasma is proposed and analyzed using Silvaco TCAD simulation software. The proposed device will be worked as a transducer sensor which is based upon the principle of the electrostatic charge plasma. The inclusion of doping less charge plasma will ease the device in terms of cost production and form random dopant fluctuation (RDF). The inclusion of charge plasma with gate stacking will enhance the electrostatics control over the gate in order to gain the variation of drain current to boost the current sensitivity. The selection width of the High-K dielectric constant material with SiO2 will filter out using equivalent gate oxide thickness. The physics behind the change is work function of the gate material in the presence of the gas material is the dissociation and absorption of gas molecule via diffusion process to the catalytic gate metal of the device. In addition, n + SiGe pocket layer is introducing to suppress the tunneling barrier at source channel interface due to reduction in the band gap energy material from 1.1 to 0.7 eV. This paper analysis with oxygen and ammonia gases forms different introduced gate metal electrode such as Silver (m1 = 4.26–4.46 eV), Molybdenum (m2 = 4.40–4.60 eV), Ruthenium (m3 = 4.71–4.91 eV), and Cobalt (m4 = 5.0–5.20 eV). In this regard, the current sensitivity, electric filed, surface potential, energy band gap and other electrical characteristics with different drain and gate bias with suitable range is operated. The vertical distribution of the channel concentration will improve the device scalability. To test changes in device sensitivity of the catalytic material of the gate electrode will increases as a work function with the range of 50, 100, 150, 200, and 250 meV. The reported sensitivity (Idon/Idoff) is higher for lower work function i.e. for Silver, Cobalt, Molybdenum and Ruthenium the sensitivity is 4.18 × 102, 3.49 × 102, 1.02 × 103 and 2.79 × 101 respectively.