Showing papers on "Multiplexer published in 2021"

Data Conversion Handbook

Abstract: 1. Fundamentals of Sampled Data Systems Coding and Quantizing DAC/ADC Ideal Static Transfer Functions Sampling Theory Data Converter AC errors and specifications 2. DAC Architectures and Origins Kelvin Divider String DACs R/2R DACs Segmented DACs Capacitor DACs Multiplying DACs Interpolating DACs Deglitching DAC outputs PWM DACs Sigma-Delta DACs Video DACs with lookup tables Digital potentiometers MicroDACs LogDACs 3. ADC Architectures and origins Low speed High speed Sigma-Delta 4. Data Converter Process Technology 5. Testing Data Converters 6. Interfacing to ADCs and DACs 7. Data Conversion Support Circuits Sample-and-hold circuits Voltage references Analog switches and multiplexers 8. Applications Precision measurement and sensor conditioning Data acquisition subsystems Multichannel systems and multiplexing Data distribution systems using multiple DACs Digital pot applications Display electronics Audio Video Software radio and IF sampling Higher levels of integration DDS 9. Hardware Design Techniques for Mixed-Signal Systems Passive components Printed circuit board design issues Layout "Smart" Partitioning Grounding mixed signal devices Digital isolation techniques Filtering switching supply outputs Data converter overvoltage protection Thermal considerations EMI/RFI considerations Logic considerations Simulation and IBIS models Prototyping Evaluation Boards Appendix Index

Inverse-design magnonic devices.

Abstract: The field of magnonics offers a new type of low-power information processing, in which magnons, the quanta of spin waves, carry and process data instead of electrons. Many magnonic devices were demonstrated recently, but the development of each of them requires specialized investigations and, usually, one device design is suitable for one function only. Here, we introduce the method of inverse-design magnonics, in which any functionality can be specified first, and a feedback-based computational algorithm is used to obtain the device design. We validate this method using the means of micromagnetic simulations. Our proof-of-concept prototype is based on a rectangular ferromagnetic area that can be patterned using square-shaped voids. To demonstrate the universality of this approach, we explore linear, nonlinear and nonreciprocal magnonic functionalities and use the same algorithm to create a magnonic (de-)multiplexer, a nonlinear switch and a circulator. Thus, inverse-design magnonics can be used to develop highly efficient rf applications as well as Boolean and neuromorphic computing building blocks. Inverse design is a recent development in photonics, where by locally controlling the refractive index in a matrix, nearly any information processing functionality can be achieved. Here, Wang et al. present a scheme for inverse design for spin-waves, magnons, which have a variety of unique advantages, such as short wavelength, and large non-linearity.

A 200-225-GHz Manifold-Coupled Multiplexer Utilizing Metal Waveguides

Abstract: This article presents a 220-GHz four-channel, noncontiguous, and manifold-coupled waveguide multiplexer for future terahertz (THz) multichannel communication application. The multiplexer is composed of four Chebyshev bandpass filters based on metal waveguide technology. Through a unique design in which the tuning dimensional variables are reduced to 14 and a co-design of low-order electromagnetic (EM) distributed models and full-wave EM models, the design optimization is achieved with a good computational efficiency and design accuracy. The proposed multiplexer is fabricated by high-precision computer numerical control (CNC) milling technology, in which the fabrication errors are evaluated to be within ±3 μm. The measured results exhibit 1.7 dB of in-band insertion loss and better than 15 dB of average common-port return loss for each of the channel filter. The measured results are all in good agreement with the simulated ones, thereby validating the complete design procedure.

Cylindrical vector beam multiplexer/demultiplexer using off-axis polarization control.

Abstract: The emergence of cylindrical vector beam (CVB) multiplexing has opened new avenues for high-capacity optical communication. Although several configurations have been developed to couple/separate CVBs, the CVB multiplexer/demultiplexer remains elusive due to lack of effective off-axis polarization control technologies. Here we report a straightforward approach to realize off-axis polarization control for CVB multiplexing/demultiplexing based on a metal–dielectric–metal metasurface. We show that the left- and right-handed circularly polarized (LHCP/RHCP) components of CVBs are independently modulated via spin-to-orbit interactions by the properly designed metasurface, and then simultaneously multiplexed and demultiplexed due to the reversibility of light path and the conservation of vector mode. We also show that the proposed multiplexers/demultiplexers are broadband (from 1310 to 1625 nm) and compatible with wavelength-division-multiplexing. As a proof of concept, we successfully demonstrate a four-channel CVB multiplexing communication, combining wavelength-division-multiplexing and polarization-division-multiplexing with a transmission rate of 1.56 Tbit/s and a bit-error-rate of 10−6 at the receive power of −21.6 dBm. This study paves the way for CVB multiplexing/demultiplexing and may benefit high-capacity CVB communication.

Efficient designs of quantum-dot cellular automata multiplexer and RAM with physical proof along with power analysis

Abstract: In this manuscript, we first suggest a single-layer 2:1 QCA MUX with an ultra-low number of cells and high speed. Unlike existing designs, the output of the proposed design does not comply with the Boolean regulation and is produced using the essential characteristics of quantum technology. Single-layer 4:1 and 8:1 QCA multiplexers have also been implemented. Moreover, using the proposed 2:1 QCA MUX, a novel and efficient QCA RAM memory cell with the set and reset abilities has been proposed. Forasmuch as the most significant challenge in quantum-dot cellular automata circuit design is the number of cell counts and occupied area. The proposed 2:1 QCA MUX includes 10 cells and an occupied area of 0.03. The unique advantage of the proposed design over all previous output generation tasks is based on cellular interactions. Our findings showed that the proposed 2:1 QCA MUX has a 16.66% and 60% improvement in terms of cell count and occupied area, respectively. In order to confirm the function of the proposed design, some physical proofs are presented. The software for implement of the circuits and their power analysis are QCADesigner 2.0.3 and QCAPro, respectively. The results of the comparisons indicate that the proposed structures are more efficient than the existing ones. The QCAPro power analysis tool has been used for analyzing the power consumption of the proposed designs.

A Modularized Bidirectional Charge Equalizer for Series-Connected Cell Strings

Abstract: In this article, a modularized charge equalizer is proposed In the proposed topology, N series cells are divided into K modules and each module consists of J series cells and its multiplexer switches A multioutput transformer is used as temporary energy storage Each of the transformer outputs is connected to one of the K modules and targets the cells in its module In this way, at the same time K cells are targeted simultaneously and the speed of balancing has increased In the proposed circuit, energy can be transferred by string to cell, cell to string, and cell to cell methods In addition, it can be transferred between modules and equalize them Therefore, the proposed topology is very flexible and can circumvent the limitations of each method and use the appropriate method in the right place Also, a step-by-step method for command the multiplex switches is proposed To illustrate the correctness of the circuit operation, a prototype is implemented to balance the charge of four lithium-ion battery cells The experimental results confirm the correctness of the proposed circuit operation

Polarization-transparent silicon photonic add-drop multiplexer with wideband hitless tuneability.

Abstract: Flexible optical networks require reconfigurable devices with operation on a wavelength range of several tens of nanometers, hitless tuneability (i.e. transparency to other channels during reconfiguration), and polarization independence. All these requirements have not been achieved yet in a single photonic integrated device and this is the reason why the potential of integrated photonics is still largely unexploited in the nodes of optical communication networks. Here we report on a fully-reconfigurable add-drop silicon photonic filter, which can be tuned well beyond the extended C-band (almost 100 nm) in a complete hitless (>35 dB channel isolation) and polarization transparent (1.2 dB polarization dependent loss) way. This achievement is the result of blended strategies applied to the design, calibration, tuning and control of the device. Transmission quality assessment on dual polarization 100 Gbit/s (QPSK) and 200 Gbit/s (16-QAM) signals demonstrates the suitability for dynamic bandwidth allocation in core networks, backhaul networks, intra- and inter-datacenter interconnects. Reconfigurable wavelength-selective devices are essential components of flexible optical networks. Here the authors show a silicon-photonic add-drop multiplexer meeting the strict requirements of telecom systems in terms of broadband operation range, hitless tunability and polarization transparency.

Fabrication-Tolerant CWDM (de)Multiplexer Based on Cascaded Mach–Zehnder Interferometers on Silicon-on-Insulator

Abstract: We demonstrate a cascaded Mach–Zehnder interferometer (MZI) based coarse wavelength division multiplexing (CWDM) (de)multiplexer on silicon-on-insulator with its spectral responses well aligned to the defined wavelength grids and are highly tolerant to the manufacturing linewidth variability. This was achieved by optimizing the waveguide widths and lengths of two arms in every MZI. As-realized CWDM (de)multiplexer exhibits a spectral shift of 0.487 nm, an insertion loss of less than 2.1 dB, and a channel crosstalk of lower than −20 dB, while reference devices fabricated on the same chips suffer from serious spectral shift of 15.4 nm to the shorter wavelength and higher insertion loss/channel crosstalk. The proposed MZI design concept can be applied to all MZI-based photonic devices and related photonic integrated circuits, so this work validates a promising design path towards practical WDM applications on silicon-on-insulator.

Designing nanotechnology QCA–multiplexer using majority function-based NAND for quantum computing

Abstract: Quantum-dot cellular automata (QCAs) are one of the most significant state-of-the-art technologies that have exhibited the potential to replace the complementary metal oxide semiconductor. QCA offers a variety of benefits over its conventional counterpart, including size, latency, and energy consumption. Meanwhile, multiplexers are crucial to the design of arithmetic and logic circuits, and NOT-AND (NAND) gates are universal gates that allow the design of any circuit. In this paper, we propose a new multiplexer based on three NAND gates in QCA. De Morgan's law is used to derive new equations and to design multiplexers using only NAND logics. The proposed circuit is designed and verified not only to minimize time and space complexity but also to minimize energy loss. Finally, we design an arithmetic circuit that is capable of performing various operations using the proposed multiplexer.

Cognitive and autonomous QoT-driven optical line controller

Abstract: In the direction of disaggregated and cognitive optical networks, this work proposes and experimentally tests a vendor-agnostic optical line controller architecture capable of autonomously setting the working point of optical amplifiers to maximize the capacity of a ROADM-to-ROADM (reconfigurable optical add–drop multiplexer) link. From a procedural point of view, once the equipment is installed, the presented software framework performs an automatic characterization of the line, span by span, to abstract the properties of the physical layer. This process requires the exploitation of monitoring devices such as optical channel monitors and optical time domain reflectometers, available, in a future perspective, in each amplification site. On the basis of this information, an optimization algorithm determines the working point of each amplifier to maximize the quality of transmission (QoT) over the entire band. The optical line controller has been experimentally tested in the laboratory using two different control strategies, achieving in both cases a homogeneous QoT for each channel close to the maximum average and an excellent match with respect to emulation results. In this framework, the Gaussian noise simulation in Python (GNPy) open source Python library is used as the physical model for optical propagation through the fiber, and the covariance matrix adaptation evolution strategy is used as an optimization algorithm to identify properties of each fiber span and to maximize the link capacity.

Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V V DD Digital Logic Circuits

Abstract: The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high ION/IOFF of 1016, possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of tFE on noise margin and read-write delay, operated at 0.4 VDD. The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.

Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks

Abstract: Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been introduced to challenge the security foundations of locking schemes. These attacks are able to recover a significant percentage of the key without having access to an activated circuit. This paper address this issue through two focal points. First, we present a theoretical model to test locking schemes for key-related structural leakage that can be exploited by machine learning. Second, based on the theoretical model, we introduce D-MUX: a deceptive multiplexer-based logic-locking scheme that is resilient against structure-exploiting machine learning attacks. Through the design of D-MUX, we uncover a major fallacy in existing multiplexer-based locking schemes in the form of a structural-analysis attack. Finally, an extensive cost evaluation of D-MUX is presented. To the best of our knowledge, D-MUX is the first machine-learning-resilient locking scheme capable of protecting against all known learning-based attacks. Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning.

A microwave SQUID multiplexer optimized for bolometric applications

Abstract: A microwave superconducting quantum interference device multiplexer has been optimized for reading out large arrays of superconducting transition-edge sensor (TES) bolometers. We present the scalable cryogenic multiplexer chip design that may be used to construct an 1820-channel multiplexer for the 4–8 GHz rf band. The key metrics of yield, sensitivity, and crosstalk are determined through measurements of 455 readout channels, which span 4–5 GHz. The median white-noise level is 45 pA/ Hz, evaluated at 2 Hz, with a 1/f knee ≤ 20 mHz after common-mode subtraction. The white-noise level decreases the sensitivity of a TES bolometer optimized for detection of the cosmic microwave background at 150 GHz by only 3%. The measured crosstalk between any channel pair is ≤ 0.3%.

Reconfigurable Fiber Wireless IFoF Fronthaul With 60 GHz Phased Array Antenna and Silicon Photonic ROADM for 5G mmWave C-RANs

Abstract: We demonstrate experimentally a bandwidth-reconfigurable mmWave Fiber Wireless (FiWi) fronthaul bus topology for spectrally efficient and flexibly reconfigurable 5G Centralized-Radio Access Networks (C-RAN). The proposed fronthaul architecture includes four 1 Gb/s Intermediate Frequency over Fiber (IFoF) channels that can be flexibly allocated among two in-series Reconfigurable Optical Add/Drop Multiplexer (ROADM) integrated nodes, supporting in total 8 V-band 32-element Phased Array Antenna (PAA) terminals. The ROADM was fabricated as an integrated photonic device exploiting the ultra-low loss Si3N4 TriPleX waveguide integration platform and an architectural layout based on cascaded MZI interleavers. The device has flat top response of 32.5 GHz with a Free Spectral Range (FSR) of 100 GHz and fiber-to-fiber losses of 5 dB, while the V-band PAA supports analog RF beamsteering capabilities within a 90°-sector and 1m wireless distance. Each of the FiWi links carries a 250 MBd QAM16 waveform enabling a total of 1 Gb/s rate per end user beam, complying with the 5G Key Performance Indicator (KPI) user-rate requirement. Bandwidth-reconfigurability is experimentally demonstrated by selectively dropping channels either at the first or at the second ROADM node, allowing in this way the bandwidth allocation to be flexibly defined between two different network segments. Both uplink and downlink performance are experimentally validated for different ratios of bandwidth allocation among the two nodes, revealing Error Vector Magnitude (EVM) values that meet the respective 3GPP signal quality specifications. The two-stage FiWi IFoF/mmWave fronthaul bus topology, based on a miniaturized, integrated, low loss Si3N4 ROADM and supporting high-capacity wireless beamsteering capability can form a promising roadmap towards flexible and reconfigurable 5G C-RAN architectures.

>100-GHz Bandwidth Directly-Modulated Lasers and Adaptive Entropy Loading for Energy-Efficient >300-Gbps/λ IM/DD Systems

Abstract: We demonstrate DML-based net 325-Gb/s at back-to-back and 321.24-Gb/s after 2-km standard single-mode fiber transmissions for >300-Gbps/λ short-reach optical interconnects. Our net rate performance denotes an increase of ∼34% compared to our previous works, while the pre-FEC rates are >400 Gbps. The DML transmitter is based on a PPR-enhanced, >100-GHz-bandwidth DML, fabricated by our novel membrane-III-V-on-SiC technology. Also wide-band, entropy-loaded DMT modulation is utilized based on a novel adaptive algorithm and via a digitally-preprocessed analog multiplexer. These results pave the way towards low-cost and energy-efficient Terabit Ethernet and a significant step towards achieving DML-based 400-Gbps/λ IM/DD systems in the future.

Ultra-Compact Mode-Division Multiplexed Photonic Integrated Circuit for Dual Polarizations

Abstract: Polarization and mode division multiplexing are powerful tools for large-capacity parallel optical communications. Dual-polarization and mode-division multiplexed silicon photonic integrated circuit with ultra-small footprint is proposed and experimentally demonstrated. The circuits consist of a mode multiplexer, 3-dB power splitter and two demultiplexers which can simultaneously handle TE0, TE1, TM0 and TM1 mode. Compared with conventional device structure, the device footprint is scaled down via pixelated waveguide meta-structure. The mode multiplexer and the splitter have a footprint of only 6.8 μm × 6 μm and 6 μm × 5.25 μm, respectively. The fabrication tolerance on the nanohole size variations are studied, and the fabricated devices are systematically characterized. The measured insertion losses of the multiplexer and 3-dB power splitter are below 1.4 dB and 4.5 dB for all four modes within the wavelength range from 1530 nm-1570 nm. In the meantime, the measured maximum inter-mode cross talk is below -15 dB over a 30 nm bandwidth. The experimental results also indicate the power imbalance of the splitter is within 0.4 dB from 1530 nm-1570 nm. Since the demonstrated polarization and mode handling devices via pixelated meta-structures occupy significantly smaller chip area than conventional wisdoms, this work shows the potential for large scale and dense integration of polarization and mode division multiplexing system on photonic chip.

High Performance Error Tolerant Adders for Image Processing Applications

Abstract: In this paper, we proposed High Performance Error Tolerant Adders (HPETA) which have an efficient design and quality metrics for inexact computing applications. To achieve high performance, Multipl...

Gratingless integrated tunneling multiplexer for terahertz waves

Abstract: The arrayed waveguide grating (AWG) is a versatile and scalable passive photonic multiplexer that sees widespread usage. However, the necessity of a waveguide array engenders large device size, and gratings invariably commute finite power into undesired diffraction orders. Here, we demonstrate AWG-like functionality without a grating or waveguide array, yielding benefits to compactness, bandwidth, and efficiency. To this end, we exploit optical tunneling from a dielectric waveguide to an adjacent slab in order to realize a slab-confined frequency-scanning beam, which is manipulated using in-slab beamforming techniques that we have developed in order to separate distinct frequency bands. In this way, we devise an all-intrinsic-silicon integrated $4 \times 1$ frequency-division terahertz multiplexer, which is shown to support aggregate data rates up to 48 Gbit/s with an on–off-keying modulation scheme, operating in the vicinity of 350 GHz. Our investigation targets the terahertz range, to provide a critical missing building block for future high-volume wireless communications networks.

Electro-optic reconfigurable two-mode (de)multiplexer on thin-film lithium niobate

Abstract: We propose and demonstrate a compact electro-optic reconfigurable two-mode (de)multiplexer using the configuration of cascaded Mach–Zehnder interferometers formed on thin-film X-cut lithium niobate on silica. Our fabricated device, which is 9.5-mm long, can spatially switch between the two transverse-electric modes with an efficiency higher than 98% from 1530–1560 nm and beyond at an applied voltage of 6.5 V. The switching speed is faster than 30 ns. Our proposed mode switch could find applications in fiber-based and on-chip mode-division-multiplexing systems.

Bit-swapping linear feedback shift register (LFSR) for power reduction using pre-charged XOR with multiplexer technique in built in self-test

Abstract: Testing becomes an inevitable part of the VLSI circuit All the circuits or products must be verified before delivery The data collected during testing is used to remove the faulty parts from the products and help to enhance the design and manufacturing process and improve the returns as well There are several contributions made by researchers which are majorly based on Linear Feedback Shift Register (LFSR), bit swapping LFSR and dual threshold bit swapping LFSR methods Reduction of delay, power consumptions and fault coverage are considered as major factors from the above methods The proposed approach uses Bit Swapping-Linear Feedback Shift Register (BS-LFSR) architecture which integrates pre-charge, set-reset and gate replacement with mux techniques have alleviated the inherent drawbacks of linear feedback shift register and produced better results Pre-charge method is reducing the delay and power consumption there by maximizing the operating frequency angle with high performance High fault coverage is achieved through set and reset technique Multiplexers mainly employed to minimize the delay and power consumption BS-LFSR pattern generators are used to decrease the transition power from high switching action These are producing an arbitrary test sequences with less power of switching by determining the pretense space between two subsequent designs The area is reduced with the help of combinational logic Experimental evaluation is done using ISCAS89 benchmark datasets From the results, it is inferred that the fault coverage is increased and power consumptions are reduced

A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler

Abstract: The rapid surge of data transmission within computation, storage and communication infrastructures is pushing the speed boundary of traditional copper-based electrical links. Recent realizations of l00Gb/s wired links require advanced FinFET technologies, highcost packaging/cables and power-consuming equalization. High-frequency waves over dielectric waveguides have been considered as an alternative solution that exploits the low-loss, broadband medium while maintaining compatibility with existing silicon 1C platforms. However, since its debut in 2011 [1], this scheme, previously using $\leq 140\mathrm{G}\mathrm{H}\mathrm{z}$ carriers, has only achieved data rates of up to 36Gb/s[2]. lt is expected that higher carrier frequencies (e.g. >200GHz) and multi-channel aggregation would further increase the data rate while shrinking the interconnect size; but that scheme has been hindered by challenges related to the required high-order multiplexer and ultra-broadband waveguide coupler operating efficiently at sub terahertz (sub-THz) frequencies. in this paper, using a 130nmSiGe BiCMOS technology, we present a multi-channel, multiplexer/coupler-integrated transmitter (Tx) that delivers a data rate of $105\mathrm{G}\mathrm{b}/\mathrm{s}(3\times 35\mathrm{G}\mathrm{b}/\mathrm{s})$. To demodulate each channel, a 35Gb/s coupler-integrated receiver (Rx) is also developed. Ourlink, including the chipset and a 0. 4mm-wide, 30cm-long dielectric ribbon, experimentally demonstrates the potential speed, efficiency, size and cost advantages of THz fiber links in high-speed inter-server and backplane fabrics.

A 5G Fiber Wireless 4Gb/s WDM Fronthaul for Flexible 360° Coverage in V-Band massive MIMO Small Cells

Abstract: Towards relieving the bandwidth limitations in 5G mobile fronthaul networks, a Fiber Wireless (FiWi) small cell architecture is presented, relying on spectrally efficient analog transport on intermediate frequency over fiber (IFoF) and a millimeter wave (mmWave) phased array antenna (PAA) interfaced with a low-loss optical add/drop multiplexer (OADM) on Si3N4/SiO2 TriPleX platform with 5 dB fiber-to-fiber losses. Specifically, four 1 Gb/s FiWi links, each carrying a 250 MBd 16-QAM signal on 5.8 GHz IFoF, are wavelength division multiplexed (WDM) and transported across a 10 km Single Mode Fiber (SMF), before being demultiplexed into the constituent channels in the OADM device and subsequently wirelessly transmitted by the PAA over a 1 m-long V-band link with 90° degree beamsteering capability. Featuring 4x 1Gb/s user rate with beamsteering to meet the respective 5G key performance indicator (KPI) for the peak user rate and an EVM within the acceptable 3GPP limit of 12.5%, the current work forms the first centralized FiWi point-to-multipoint small cell architecture with efficient transport scheme on IFoF and ubiquitous 360°-degree coverage for emerging 5G mmWave networks.

Tunable Orbital Angular Momentum Converter Based on Integrated Multiplexers

Abstract: A four-orbital angular momentum (OAM) modes converter consisting of the cascade of an OAM demultiplexer and an OAM multiplexer is implemented and characterized. The OAM multiplexer is realized with an integrated photonic circuit based on four tunable OAM emitters, i.e. the order of the emitted OAM mode can be selected by thermal tuning. It works on linearly polarized signals. The OAM demultiplexer, completely passive, consists of the cascade of two patterned refractive elements followed by a lens and can work independently of the polarization of the input signals. The proposed OAM converter can receive at its input a bundle of spatially multiplexed beams mapped on different OAM modes, each one carrying a set of wavelength division multiplexed (WDM) channels. Each WDM channel can be independently converted to a different OAM mode and all the OAM beams are multiplexed at the converter output. The performance of the proposed scheme is assessed as a function of the order of the OAM beam before and after the conversion, as well as of the wavelength of the input signal. The measurements show a power penalty on the bit error-rate (BER) curves of less than 1 dB in all the considered cases. The scheme is tested also with 100 Gb/s real data-traffic generated with commercial network cards, showing full operability. The cascading ability of the proposed scheme is also investigated in an experiment where the signal to be converted is generated by an OAM multiplexer, i.e. the output stage of the OAM converter, showing a penalty of less than 2 dB. Moreover, considerations on scalability, bandwidth and power consumption are also included along with a possible application of OAM conversion within add/drop nodes in an OAM-wavelength multiplexed transmission scenario.

Radio-over-free space optical space division multiplexing system using 3-core photonic crystal fiber mode group multiplexers

Abstract: Radio over free space optics (Ro-FSO) systems have previously relied on the signal intensity, wavelength and polarization for multiplexing data streams in order to increase to the signal quality and achievable link range. This work leverages on optical space division multiplexing by using novel three-core photonic crystal fiber (PCF) mode group multiplexers and hexagonal mid-gapped tiered PCF mode group equalizers for improving the signal quality and increasing the achievable link range in a rural environment. At the transmitter, a three-core PCF mode group demultiplexer converts the fundamental mode into three distinct mode groups used as carriers for independent transmission of three radio frequency signals. At the receiver, the three PCF successfully equalizes the power from the received signal, with the channel impulse responses showing an improvement in the signal quality. An increment between 13.6% and 31.1% in the achievable link range for all channels is evident under medium and heavy fog conditions at the same bit error rate level, using the designed PCF mode group multiplexers and equalizers.

24 [1×12] Wavelength Selective Switches Integrated on a Single 4k LCoS Device

Abstract: This article demonstrates the design, assembly, optimisation, and characterisation of 24 [1 × 12] wavelength selective switches (WSSs) based on a single set of optics and a 4k liquid crystal on silicon (LCoS) device. The average insertion loss was measured to be 8.4 dB with an average crosstalk level of 26.9 dB. To our knowledge, this module with 312 fibre ports is the highest-capacity WSS demonstrated so far. The module can be flexibly reconfigured into different switches and port counts for advanced reconfigurable optical add/drop multiplexer (ROADM) applications.

An Efficient Hardware Design for Accelerating Sparse CNNs with NAS-based Models

Abstract: Deep convolutional neural networks (CNNs) have achieved remarkable performance at the cost of huge computation. As the CNN models become more complex and deeper, compressing CNNs to sparse by pruning the redundant connection in the networks has emerged as an attractive approach to reduce the amount of computation and memory requirement. On the other hand, FPGAs have been demonstrated to be an effective hardware platform to accelerate CNN inference. However, most existing FPGA accelerators focus on dense CNN models which are inefficient when executing sparse models as most of the arithmetic operations involve addition and multiplication with zero operands. In this work, we propose an accelerator with software-hardware co-design for sparse CNNs on FPGAs. To efficiently deal with the irregular connections in the sparse convolutional layers, we propose a weight-oriented dataflow that exploits element-matrix multiplication as the key operation. Each weight is processed individually which yields low decoding overhead. Then we design an FPGA accelerator that features a tile look-up table (TLUT) and a channel multiplexer (CMUX). The tile look-up table is designed to match the index between sparse weights and input pixels. Using TLUT, the runtime decoding overhead is mitigated by using an efficient indexing operation. Moreover, we propose a weight layout to enable efficient on-chip memory access without conflicts. To cooperate with the weight layout, a channel multiplexer is inserted to locate the address. Last, we build a Neural Architecture Search (NAS) engine that leverages the reconfigurability of FPGAs to generate an efficient CNN model and choose the optimal hardware design parameters. Experiments demonstrate that our accelerator can achieve 223.4-309.0 GOP/s for the modern CNNs on Xilinx ZCU102, which provides a 2.4X-12.9X speedup over previous dense CNN accelerators on FPGAs. Our FPGA-aware NAS approach shows 2X speedup over MobileNetV2 with 1.5% accuracy loss.