Showing papers on "p–n junction published in 2001"

An efficient room-temperature silicon-based light-emitting diode.

Abstract: There is an urgent requirement for an optical emitter that is compatible with standard, silicon-based ultra-large-scale integration (ULSI) technology. Bulk silicon has an indirect energy bandgap and is therefore highly inefficient as a light source, necessitating the use of other materials for the optical emitters. However, the introduction of these materials is usually incompatible with the strict processing requirements of existing ULSI technologies. Moreover, as the length scale of the devices decreases, electrons will spend increasingly more of their time in the connections between components; this interconnectivity problem could restrict further increases in computer chip processing power and speed in as little as five years. Many efforts have therefore been directed, with varying degrees of success, to engineering silicon-based materials that are efficient light emitters. Here, we describe the fabrication, using standard silicon processing techniques, of a silicon light-emitting diode (LED) that operates efficiently at room temperature. Boron is implanted into silicon both as a dopant to form a p-n junction, as well as a means of introducing dislocation loops. The dislocation loops introduce a local strain field, which modifies the band structure and provides spatial confinement of the charge carriers. It is this spatial confinement which allows room-temperature electroluminescence at the band-edge. This device strategy is highly compatible with ULSI technology, as boron ion implantation is already used as a standard method for the fabrication of silicon devices.

Ultraviolet Emission From a Diamond Pn Junction

Abstract: We report the realization of an ultraviolet light–emitting diode with the use of a diamond pn junction. The pn junction was formed from a boron-doped p-type diamond layer and phosphorus-doped n-type diamond layer grown epitaxially on the {111} surface of single crystalline diamond. The pn junction exhibited good diode characteristics, and at forward bias of about 20 volts strong ultraviolet light emission at 235 nanometers was observed and was attributed to free exciton recombination.

Current crowding in GaN/InGaN light emitting diodes on insulating substrates

Abstract: GaN/InGaN light emitting diodes (LEDs) grown on sapphire substrates have current transport along the lateral direction due to the insulating nature of the substrate. The finite resistance of the n-type GaN buffer layer causes the pn junction current to be nonuniform and “crowd” near the edge of the contact. The current-crowding effect is analyzed both theoretically and experimentally for p-side-up mesa structure GaN/InGaN LEDs. The calculation yields an exponential decay of the current distribution under the p-type contact with a characteristic current spreading length, Ls. It is shown that GaN/InGaN LEDs with high p-type contact resistance and p-type confinement layer resistivity have a relatively uniform current distribution. However, as the p-type GaN conductivity and p-type ohmic contact conductivity is improved, significant current crowding near the contact edge will occur. The current crowding effect is analyzed experimentally in GaN/InGaN LEDs emitting in the blue spectral range. Experimental resul...

Silicon carbide semiconductor device and manufacturing method thereof

Abstract: In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n - -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

Field effect transistor having a lateral depletion structure

Abstract: A field effect transistor device and a method for making a field effect transistor device are disclosed. The field effect transistor device includes a stripe trench extending from the major surface of a semiconductor substrate into the semiconductor substrate to a predetermined depth. The stripe trench contains a semiconductor material of the second conductivity type to form a PN junction at an interface formed with the semiconductor substrate.

Semiconductor memory device with floating storage bulk region and method of manufacturing the same

Abstract: A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

"Paradoxes" of carrier lifetime measurements in high-voltage SiC diodes

Abstract: For Silicon Carbide (SiC) high-voltage rectifier diodes, contradictions appear when the most important parameter of the diodes, the minority carrier lifetime, is measured by different techniques. A qualitative analysis and a computer simulation have been carried out to clarify the origin of these contradictions. For 4H-SiC p/sup +/n diodes with 6 kV blocking capability, data on residual voltage drop at high current densities, switch-on time, reverse current recovery, and post-injection voltage decay are analyzed. It is shown that the whole set of experimental data can be explained by the existence of a thin (l/spl sim/0.1 /spl mu/m) layer near the metallurgical boundary of the p/sup +/n junction with very small carrier lifetime /spl tau//sub l/ that is essentially smaller than the carrier lifetime /spl tau/ across the remaining part of the 50-/spl mu/m n-base. It is emphasized that the existence of such a layer allows, under certain conditions, the combination of a relatively low residual forward voltage drop and very fast reverse recovery. Approaches to minority carrier lifetime measurements are discussed.

Semiconductor integrated circuit device and manufacturing method thereof

Abstract: In the semiconductor integrated circuit device, a first P + type buried layer formed as an anode region and an N + type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.

Investigation of the bonding strength and interface current of p-Si/n-GaAs wafers bonded by surface activated bonding at room temperature

Abstract: Equivalent bulk strength of the interface between p-Si/n-GaAs bonded through the surface activated bonding (SAB) method is found. The interface current was extensively investigated. Nonideal behavior of the pn junction current is found to be due to the tunneling current between the conduction band and valence band across the transition region associated with band gap states. Interface current decreases with increasing sputtering time and energy and vice versa. Irradiation time and energy dependent behavior indicates that the accumulation of radiation induced defects associated with the doping controls the interface current of p-Si/n-GaAs. Moreover, strong impact of the exposure to an ultrahigh vacuum atmosphere of the activated surfaces on the interface current of p-Si/p-Si is found. Finally it can be suggested that a laser diode can be fabricated by the bonding between p-Si and n-GaAs through the SAB method, because of the achievement of equivalent bulk strength of the interface.

Production and properties of p–n junctions in reactively sputtered ZnO

Abstract: In order to develop electroluminescent and laser devices based on the ultraviolet exciton emission of ZnO, it will be important to fabricate good p–n junctions. As-grown ZnO is normally n-type because of intrinsic donor defects such as oxygen vacancies and zinc interstitials, or unintended hydrogen. Making p-type ZnO has been more difficult, possibly due to self-compensation by easily formed donor defects. In this work, we demonstrate that reactively sputtered, annealed ZnO films can be changed from n-type to moderate p-type by adjusting the oxygen/argon ratio in the sputtering plasma. We report the properties of p–n homojunctions fabricated in this way, and characterize transport in the films by the Hall measurements. Ohmic contacts were formed by deposition of Au/Al films. Our finding of p-type conductivity in apparently intrinsic ZnO formed by reactive sputtering is not inconsistent with calculated defect formation enthalpies if account is taken of the higher chemical potential of the dissociated oxygen reservoir represented by the sputter plasma, compared to the molecular oxygen reservoir assumed in the calculation of formation enthalpies. If hydrogen turns out to be the main compensating donor, the role of oxygen pressure in controlling incorporation of background hydrogen during sputtering may also be implicated.

High efficient pn junction solar cell

Abstract: A pn junction solar cell includes a pn junction structure including a p-type and a n-type semiconducting layer, a front contact electrode formed on the front surface of the pn junction structure through a contact pattern having a constant width, and a rear contact electrode formed on a rear surface of the pn structure. The front contact electrode is reduced in its width as it goes away from a terminal.

Photoelectric converting device

Abstract: A photoelectric converting device is provided with enhanced photoelectric conversion efficiency by optimizing a combination of materials used for top and bottom cells. The photoelectric converting device of the present invention is provided with first and second pn junctions. The first pn junction is formed in a semiconductor substantially represented by (Al 1−y Ga y ) 1−x In x P, and the second pn junction is formed in a semiconductor substantially represented by Ga 1−z In z As.

Electrical spin injection in ferromagnetic//nonmagnetic semiconductor heterostructures

Abstract: Magneto-electroluminescence properties of ferromagnetic/nonmagnetic semiconductor pn junction light emitting diodes (LEDs) are presented. A ferromagnetic p-type (Ga,Mn)As layer is grown on i-(In,Ga)As quantum well (QW)/n-GaAs so that the degree of spin polarization of holes injected from (Ga,Mn)As into GaAs can be probed by analyzing the polarization of light emitted from the LED structures. The EL polarization as a function of magnetic field exhibits clear hysteresis below the ferromagnetic transition temperature of (Ga,Mn)As, which is the evidence that spin-polarized electrical current is injected into nonmagnetic semiconductor.

Schottky, p-n junction diode, and pin junction diode and their manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a high breakdown voltage diode that prevents leakage current from increasing, reliably stabilizes operation, at the same time, has a high yield in making area larger, and uses silicon carbide. SOLUTION: In the Schottky diode 10, where a Schottky electrode 15 is joined to a 4H-type SiC semiconductor 13, the orientation of an SiC semiconductor 13 that comes into contact with the Schottky electrode 15 should have a 03-38} surface, or a surface at an off angle that is within 10 deg. from the surface.

Excitation of a microdischarge with a reverse-biased pn junction

Abstract: Excitation of cylindrical microdischarges, 300–360 μm in diameter, by a reverse-biased, Si pn junction has been demonstrated. Devices fabricated from commercial diodes have been operated with Ne gas pressures in the 200–700 Torr range and dc voltages as low as 120 V. For a Ne gas pressure of 700 Torr, the wavelength-integrated (300–800 nm) output power—emitted into a solid angle of ∼6×10−2 sr—of a 360-μm-diam device is 48±1 μW for an operating current and voltage of 5.7±0.1 mA and 134 V, respectively. This hybrid solid state/gas device represents the demonstration of the generation of a gas discharge by a pn junction and lends itself to the fabrication of large arrays.

Effects of interface layer on thermoelectric properties of a pn junction prepared via the BMA-HP method

Abstract: Prealloyed p and n-type bismuth telluride-based materials produced by bulk mechanical alloying are directly one-step hot-pressed to yield a thermoelectric pn junction. Variation of constitutional element concentrations across the pn interface is characterized by EPMA to determine the interface thickness of the pn junction. The electrical resistivity of the interface layer is greater than that of both p and n semiconductor materials. Analytic expressions for Seebeck coefficient and figure of merit versus interface layer size are deduced. The Seebeck coefficient of the pn junction is inversely proportional to the ratio of the interface layer length to the pn junction height (hi/h) and agrees well with experimental results. In a pn junction with an interface layer certain thickness, there is a maximum figure of merit at the optimal hi/h; with the decrease in interface thickness, the maximum increases, and correspondingly, the optimal hi/h decreases. In other words, the pn composite billet with a thinner interface layer can attain a larger figure of merit at the same hi/h than that with a thicker interface. Adjusting the process parameter, with proper cutting, thermoelectric properties can be improved greatly; this method of producing a pn junction is feasible.

Photodiode properties of epitaxial Pb(Ti, Zr)O3/SrTiO3 ferroelectric heterostructures

Abstract: A substantial photovoltaic effect is found in heterostructures of typical ferroelectric oxides. Pb(Ti, Zr)O3/Nb-doped SrTiO3, especially, exhibits current–voltage characteristics of the photovoltaic effect of a typical pn junction (p: hole carrier type, n: electron carrier type). A preliminary nonoptimized device shows high performance such as open circuit voltage of 0.7–0.8 V, external conversion efficiency of 0.6%–0.8%, and response time faster than 20 μs for ultraviolet light at room temperature, suggesting the potential of this diode as a new class of photodiode. The results support the formation of a pn like junction by ferroelectric oxides. Additionally, the photovoltaic characteristics are tuned by the application of short pulse voltages and retained.

Power semiconductor device containing at least one zener diode provided in chip periphery portion

Abstract: A Zener diode ( 11 ) is provided in a chip periphery portion (CPP) which entirely surrounds the periphery of a unit cell portion (UCP) and the periphery of a gate pad portion (GPP) along first to fourth directions (D 1 ) to (D 4 ). The Zener diode ( 11 ) has an N + -P-N + -P-N + structure consisting of an N + type layer ( 1 B), a P type layer ( 33 ), an N + type layer ( 32 ), a P type layer ( 31 ) and an N + type layer ( 1 A), in which these layers extend along the first to fourth directions (D 1 ) to (D 4 ). With this structure, (1) achieving reduction in on-state resistance through enlargement of an effective cell region by downsizing the gate pad and (2) ensuring an improvement in current-voltage characteristic of the Zener diode through an increase in PN junction width, a power semiconductor device having higher electrostatic strength is obtained.

Enhancement of minority carrier transport in forward biased GaN p-n junction

Abstract: Forward bias application to a GaN p-n junction (current density ~12 A/cm2) leads to a 1.6-fold increase in the minority electron diffusion length in the p-layer of an epitaxial p-n structure. The effect persists for several days, and is likely associated with electron injection-induced charging of Mg-related deep levels in p-type GaN.

Compound semiconductor field-effect transistor

Abstract: The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (eg InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (eg p + -GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (eg InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET

Nonvolatile memory cell with high programming efficiency

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

A fast and soft recovery diode with ultra small Qrr (USQ-Diode) using local lifetime control by He ion irradiation

Abstract: This paper presents an ultra small reverse recovery charge Qrr diode (USQ-Diode) for Insulated Gate Bipolar Transistor (IGBT) modules. The USQ-Diode has a thin p-layer anode with low impurity concentrations, p+ stripe anodes, and lifetime control by He ion irradiation. By employing the thin p-layer anode, the injection of holes into the n-layer as minority carriers was significantly reduced near the pn junction. By using the He ion irradiation, crystal defects for lifetime control were localized near the pn junction. With the combined effects from both the reduced injection of holes and the local lifetime control by the He ion irradiation, as compared to the conventional pn diode, the USQ-Diode realized such superior characteristics as 1/5 times smaller reverse recovery charge and 0.2 V lower forward voltage drop.

Semiconductor device having electrostatic protection circuit and method of fabricating the same

Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor A fourth diffusion region which makes up a Schottky diode together with the silicide layer is further provided between the silicide layer and the third diffusion region

Wavelength conversion type semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a wavelength conversion type semiconductor device for improving the reflection factor of an electrode that functions as a reflection surface and at the same time reduces contact resistance SOLUTION: The wavelength conversion type semiconductor device 10 contains a lower p-type layer 13 and an upper n-type layer 12 for composing a pn junction, a wavelength conversion material 17 that is provided at the upper portion, a first electrode 14 that is provided on the lower surface of the p-type layer and prevents excitation light from the pn junction that is electrically in contact with the p-type layer from being transmitted to the outside, and a second electrode 16 that surrounds the end face of the p-type layer and the n-type layer and is electrically in contact with only the n-type layer The wavelength conversion type semiconductor device 10 is composed so that the second electrode can be composed of a high reflection factor metal layer 16a that is made of a material having a high reflection factor near the wavelength of excitation light from the pn junction and is as thick as 10 nm or more, and a conductive transparent oxide layer 16b COPYRIGHT: (C)2002,JPO

Examination of electrostatic potential distribution across an implanted p–n junction by electron holography

Abstract: In the manufacture of semiconductor microelectronic devices, a p-n junction is formed usually by implanting a high concentration of impurity into a less heavily doped region and then heat annealing. A Si/Si p-n junction test sample has been made following the above practical process and thinned for electron holographic observation by using argon ion-milling. From the reconstructed phase image, the phase shift induced by potential drop across p-n junction can be seen clearly. To characterize quantitatively this potential drop, the mean inner potential V0 of silicon was measured precisely by electron holographic method. By measuring 25 different crystalline silicon spheres with diameter ranging from 40 to 170 nm, an average result of V0 = 12.16 +/- 0.83 V was obtained. By using this V0 value, a quantitative measurement yields the potential drop approximately 0.70 V, which is reasonably consistent with expected Si/Si junction parameter. The thickness of electric dead layer in depletion region produced from this measuring is approximately 20 nm on each sample surface.

Improved extraction of the activation energy of the leakage current in silicon p–n junction diodes

Abstract: An accurate method is proposed for the extraction of the activation energy ET from the volume generation current density JgA in silicon p–n junctions. It combines temperature-dependent current–voltage (I–V) and capacitance–voltage measurements on an array of diodes with different geometry, in order to separate the peripheral from the volume components. The JgA can be found from the volume leakage current by subtraction of the volume diffusion current JdA, which is calculated from the forward I–V characteristic. To derive the correct slope from an Arrhenius plot of the JgA, several additional corrections have been applied. One is the temperature dependence of the depletion width, which is derived from the corrected volume capacitance. The most important ET change is shown to come from the temperature dependence of the recombination lifetime.