Showing papers on "Silicon on insulator published in 2000"

Waveguiding in Planar Photonic Crystals

Abstract: Photonic crystal planar circuits designed and fabricated in silicon on silicon dioxide are demonstrated Our structures are based on two-dimensional confinement by photonic crystals in the plane of propagation, and total internal reflection to achieve confinement in the third dimension These circuits are shown to guide light at 1550 nm around sharp corners where the radius of curvature is similar to the wavelength of light

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

Abstract: We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer.

Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

Abstract: A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

Large deflection micromechanical scanning mirrors for linear scans and pattern generation

Abstract: An electrostatically driven silicon micro scanning mirror (MSM) for one-dimensional (1-D) and two-dimensional (2-D) deflection of light is presented. A special configuration of the driving electrodes allows the use of small electrode gaps without restricting the deflection of the plate geometrically. In this paper, the starting of the oscillation and the operation of the scanner is discussed. Experimental results show that scan angles of up to 60/spl deg/ can be achieved at a driving voltage of only 20 V. The 2-D deflection of a laser beam is obtained by a gimbal mounting of the mirror plate. For the fabrication of the devices, SOI-wafers are used as the base material. The mechanical structures are defined by a deep silicon etch. For the electrical isolation of areas on the movable frame, polysilicon-filled trenches are used. The mechanical stability of the scanners is tested. The devices resist shocks of more than 1000 g and show no change of the resonance frequency even after long run tests of 7/spl times/10/sup 9/ periods.

Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements

Abstract: The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.

Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device

Abstract: To decrease the thickness of a silicon thin film to a desired value without deterioration of the quality thereof while avoiding the surface roughness due to speed increasing oxidation of crystal defect portions occurring when conducting the conventional sacrificial oxidation, effect of dust particles, etc. and also avoiding deterioration of high pressure resistance of the oxide film associated with the surface roughness. A silicon ultrathin film SOI layer is produced in the following two steps: preparing a SOI wafer having a silicon thin film, which exhibits less precipitation of oxygen, thereon by the SIMOX method or the semiconductor bonding method, and cleaning the SOI wafer with an alkali solution such as SC1 and TMAH, so as to utilize the etching action of the aqueous cleaner.

Improvement of Silicon Direct Bonding Using Surfaces Activated by Hydrogen Plasma Treatment

Abstract: The silicon direct bonding process has been widely applied to silicon-on-insulator (SOI) devices, power devices, and micromechanical sensors [1–3]. This bonding technology is a feasible technique for bonding silicon wafers without the use of any adhesive material, and the bonding can be attributed to intermolecular or interatomic attractive forces between the mating surfaces [4–6]. For the success of initial bonding at room temperature, the wafer surface must be not only sufficiently clean, flat, and smooth, but also able to induce attractive forces by an appropriate surface chemistry. Commercially available direct bonding methods using wet chemical cleaning achieve surface activation by immersion in sulfuric acid solutions or alkaline solutions [7,8]. However, these wet chemical treatments have many disadvantages: they increase the possibilities of surface roughening or chemical contamination, must be customized for each substrate material, and are not appropriate for multilayer materials with different chemical reactivities [9]. This paper reports an improved method of direct wafer bonding using surfaces activated by hydrogen plasma treatment. The goal of this study was to investigate the influence of a hydrogen plasma on the bondability of silicon surfaces and on the surface chemistry and morphology. Gas-phase cleaning using a hydrogen plasma was observed to be an especially efficient way of removing carbon contaminants on the silicon surface, and the cleaned silicon surface was successfully activated.

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

Abstract: High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon

Abstract: A process for controllably forming silicon nanostructures such as a silicon quantum wire array. A silicon surface is sputtered by a uniform flow of nitrogen molecular ions in an ultrahigh vacuum so as to form a periodic wave-like relief in which the troughs of said relief are level with the silicon-insulator border of the SOI material. The ion energy, the ion incidence angle to the surface of said material, the temperature of the silicon layer, the formation depth of the wave-like relief, the height of said wave-like relief and the ion penetration range into silicon are all determined on the basis of a selected wavelength of the wave-like relief in the range 9 nm to 120 nm. A silicon nitride mask having pendant edges is used to define the area of the silicon surface on which the array is formed. Impurities are removed from the silicon surface within the mask window prior to sputtering. For the purpose of forming a silicon quantum wire array, the thickness of the SOI silicon layer is selected to be greater than the sum of said formation depth, said height and said ion penetration range, the fabrication of the silicon wires being controlled by a threshold value of a secondary ion emission signal from the SOI insulator. The nanostructure may be employed in optoelectronic and nanoelectonic devices such as a FET.

Worst-case bias during total dose irradiation of SOI transistors

Abstract: The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

Silicon on iii-v semiconductor bonding for monolithic optoelectronic integration

Abstract: In a method for bonding a silicon substrate to a III-V material substrate, a silicon substrate is contacted together with a III-V material substrate and the contacted substrates are annealed at a first temperature that is above ambient temperature, e.g. at a temperature of between about 150 °C and about 350 °C. The silicon substrate is then thinned. This bonding process enables the fabrication of thick, strain-sensitive and defect-sensitive optoelectronic devices on the optimum substrate for such, namely, a thick III-V material substrate, while enabling the fabrication of silicon electronic devices in a thin silicon layer, resulting from the thinned Si substrate, that is sufficient for such fabrication but which has been thinned to eliminate thermally-induced stress in both the Si and III-V materials. The III-V material substrate thickness thereby provides the physical strength of the composite substrate structure, while the thinned silicon substrate minimizes stress in the composite structure.

High-Efficiency Light Coupling in a Submicrometric Silicon-on-Insulator Waveguide.

Abstract: Light coupling into a sub-micrometer-thick waveguide is usually done through a grating coupler. Coupling efficiency is strongly enhanced by addition of a mirror above the grating. This new kind of coupler can be designed to achieve efficiencies as great as 80%. Numerical calculations for a high-angular-spread Gaussian incident beam are compared with experimental results obtained for a standard silicon-on-insulator waveguide.

SiC and GaN bipolar power devices

Abstract: The present status of the silicon carbide and gallium nitride bipolar power semiconductor devices is reviewed. Several unipolar and bipolar figures of merit have been examined to demonstrate the potential performance gain to be obtained from silicon carbide and gallium nitride based power devices. Several conventional as well as novel device structures have been examined, some of which have already been demonstrated and others are in their early stages of development. Conventional silicon theory has often been found to be inadequate to explain the characteristics of silicon carbide. Appropriate modifications have been applied to investigate more complicated characteristics of silicon carbide devices.

SOI device and method of fabrication

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's

Abstract: The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature in ultra-narrow MOSFET's whose channel width is less than 10 nm. This result is in excellent agreement with simulation that takes account of quantum confinement in the silicon narrow channel, indicating that the increase in threshold voltage is caused by the quantum mechanical narrow channel effect.

Handbook of semiconductor technology

Abstract: VOLUME 1 Band Theory Applied to Semiconductors Electrical and Optical Characteristics of Crystalline Semiconductors Deep Centers in Semiconductors Equilibria, Nonequilibria, Diffusion and Precipitation Dislocation Grain Boundaries Interfaces The Hall Effect in Quantum Wires Material Properties of Hydrogenated Amorphous Silicon Solubility Diffusion and Gettering of Illd Transition Elements in Silicon VOLUME 2 Silicon Processing Compound Semiconductor Processing Epitaxial Growth Photolitography Doping Etching Processes in Semiconductor Manufacturing Silicon Device Structures Compound Semicondutor Device Structures Silicon Device Processing Compound Semiconductor Device Processing Integrated Circuit Packaging Interconnect Systems

Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs

Abstract: Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities (N/sub inv/) ultra-thin SOI mobility can be higher than in heavily doped bulk MOS due a lower effective field and it is largely insensitive to silicon thickness (T/sub SI/). However, at small Ni/sub inv/ the mobility is clearly reduced for decreasing T/sub SI/. The effective mobility data are used to study the implications for ultra-short MOS transistor performance at device simulation level.

Phenomena in silicon nanostructure devices

Abstract: In nanostructures, whenever the electron mean-free-path exceeds the appropriate dimensions of the device structure, quantum natures may dictate the physical properties of devices Among many important issues, some are selected in this work, whereas others, such as the reduction of dielectric constant, the increased binding energy of dopants, etc, are discussed briefly with references for further considerations In the past several years, resonant tunneling via nanoscale silicon particles imbedded in an oxide matrix has shown striking similarity to the so-called soft breakdown (SBD), an important current subject in devices with ultrathin oxide gates The relevance in applying results discussed here to SBD is discussed A Si/O superlattice, a particular form of a new type of superlattice, semiconductor-atomic superlattice (SAS), is fully discussed This Si/O superlattice can be used in silicon quantum and light-emitting devices A diode structure with green electroluminescence has been life-tested for more than one year without degradation High-resolution TEM shows defect density below 109/cm2 Preliminary calculation shows that the Si/O complexes result in a barrier height of 09 eV for silicon, sufficient for an epitaxially grown SOI, which is potentially far better than the SOI using buried oxide implantation followed by high temperature anneal

Embedded dram on silicon-on-insulator substrate

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.

Doped silicon single electron transistors with single island characteristics

Abstract: Uniformly doped single electron transistors nominally consisting of a single island and two silicon tunneling barriers have been fabricated on silicon–on–insulator material Two operation regimes are found depending upon the gate voltages applied The structure acts either as a multiple tunnel junction device or as a single electron transistor consisting of a single dot corresponding to the geometrical shape of the device The multiple tunnel junction behavior is attributed to the formation of additional tunneling barriers, introduced into the structure by the high doping level We demonstrate that these barriers can be removed by raising the Fermi level via the application of an appropriate gate voltage

A 0.2-/spl mu/m 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

Abstract: A technology for combining 0.2-/spl mu/m self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistors (HBTs) with CMOS transistors and high-quality passive elements has been developed for use in microwave wireless and optical communication systems. The technology has been applied to fabricate devices on a 200-mm SOI wafer based on a high-resistivity substrate (SOI/HRS). The fabrication process is almost completely compatible with the existing 0.2-/spl mu/m bipolar-CMOS process because of the essential similarity of the two processes. SiGe HBTs with shallow-trench isolations (STIs) and deep-trench isolations (DTIs) and Ti-salicide electrodes exhibited high-frequency and high-speed capabilities with an f/sub max/ of 180 GHz and an ECL-gate delay of 6.7 ps, along with good controllability and reliability and high yield. A high-breakdown-voltage HBT that could produce large output swings for the interface circuit was successfully added. CMOS devices (with gate lengths of 0.25 /spl mu/m for nMOS and 0.3 /spl mu/m for pMOS) exhibited excellent subthreshold slopes. Poly-Si resistors with a quasi-layer-by-layer structure had a low temperature coefficient. Varactors were constructed from the collector-base junctions of the SiGe HBTs. MIM capacitors were formed between the first and second metal layers by using plasma SiO/sub 2/ as an insulator. High-Q octagonal spiral inductors were fabricated by using a 3-/spl mu/m thick fourth metal layer.

Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel

Abstract: We report the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si/sub 1-x/Ge/sub x//Si heterostructure channel. First, a novel lateral solid-phase epitaxy process is employed to form an ultra-thin-body that suppresses the short-channel effects. Negligible threshold voltage roll-off is observed down to a channel length of 50 nm. Second, a selective silicon implant that breaks up the interfacial oxide is shown to facilitate unilateral crystallization to form a single crystalline channel. Third, the incorporation of SiGe in the channel resulted in a 70% enhancement in the drive current.

High-quality strain-relaxed SiGe alloy grown on implanted silicon–on–insulator substrate

Abstract: We report on the growth and characterization of high-quality strain-relaxed SiGe alloys on a compliant silicon–on–insulator (SOI) substrate. The annealing temperature required for strain transfer has been reduced through boron implantation to the buried oxide, leading to a high quality SiGe alloy free from dislocations as evident from the near-band gap photoluminescence. Nearly complete strain relaxation (∼95%) for SiGe alloy of a thickness beyond the conventional critical thickness has been obtained.

Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate

Abstract: A process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate from thermally oxidized silicon wafer so that processing temperatures are limited to 900° C. is disclosed. The substrate is fabricated using H 2 split process. Processing temperatures are limited to temperature of initiating of out-diffusion of oxygen from silicon dioxide into silicon. The limit prevents deterioration of buried oxide, and the oxide has low hole trap density that is equal to the trap density of an initial thermal silicon dioxide. Processing temperatures after implantation for H 2 split process are limited to temperature of stability of dislocation microloops induced by the implantation at its damage peak. Resulting SOI structure have a gettering layer made from the microloops. The getter prevents yield drop caused by heavy metal contamination during the fabrication. Finished SOI devices have improved gate oxide integrity. Also, finished SOI circuitry has suppressed hot-electron controlled effects (backgating, transistor threshold voltage stability, side leakage). Also, radiation hardness of finished SOI devices is higher then the hardness of the SOI devices fabricated by conventional methods.

Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane

Abstract: A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs.

The development of a Novel Silicon Microdosimeter for high LET radiation therapy

Abstract: This work is the first comprehensive investigation of the issues confronting silicon microdosimetry and its application to radiotherapy. Four main problems requiring investigation are identified and addressed including requirement specification with particular emphasis on device shape, tissue equivalence, noise minimization, andsensitive volume definition. Analysis of device shape showed that a rectangular parallelepiped with a tissue equivalent converter on top of device (i.e. a silicon microdosimeter) provides a lineal energy spectrum that is closely equivalent to a sphere using the criteria of equal dose mean lineal energy. The tissue equivalent study demonstrated that under appropriate geometrical scaling (dimensions multiplied by 1/0.63) silicon detectors with well known geometry will record energy deposition spectra representative of tissue cells of equivalent shape. A novel prototype device using silicon-on-insulator (SOI) is presented. Silicon-on-insulator technology assists in defining the sensitive volume depth although the current device still suffers from lateral diffusion effects. I-V and C-V testing are performed and a noise optimization design model is presented. Methods for characterizing the collection efficiency and radiation hardness of silicon microdosimeters are presented and compared including alpha and proton microbeam spectroscopy, broadbeam alpha spectroscopy and 2D and 3D device simulation. Results from testing the low noise prototype SOI device at several high LET clinical facilities including BNCT, proton therapy and fast neutron therapy facilities are presented. In the BNCT experiments, a simultaneous thermal neutron flux and microdosimetric measurement at a high spatial resolution is demonstrated. The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rate capability and the possibility of integrating the system onto a single device with other detector types. The device also offers applicability in radiation protection and electronic single event upset (SEU) studies.

Method for fabricating a semiconductor device having recessed SOI structure

Abstract: A semiconductor device having a recessed silicon on insulator (SOI) structure includes an SOI substrate having a cell region, a peripheral region and a field region, the SOI substrate having a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, a trench in the field region of the second semiconductor layer, a device isolation film within the trench, a peripheral region recessed in the second semiconductor layer, and an active semiconductor device on the cell region and the peripheral region of the second semiconductor layer.

Transistor with local insulator structure

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Silicon-based microelectrodes for neurophysiology, micromachined from silicon-on-insulator wafers.

Abstract: A process is described for the fabrication of silicon-based microelectrodes for neurophysiology using bonded and etched-back silicon-on-insulator (BESOI) wafers. The probe shapes are defined without high levels of boron doping in the silicon; this is considered as a step towards producing probes with active electronics integrated directly beneath the electrodes. Gold electrodes, of 4μm by 4μm to 50μm by 50μm are fabricated on shanks (cantilever beams) 6μm thick and which taper to an area approximately 100μm wide and 200μm long, which are inserted into the tissue under investigation. The passive probes fabricated have been successfully employed to make acute recordings from locust peripheral nerve.

Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

Abstract: An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation. Measurements and two-dimensional simulations are used to demonstrate that the graded-channel device efficiently alleviates the parasitic BJT action, improving the breakdown voltage, by the reduction of impact ionization in the high electric field region. Based on process/device simulation and modeling, multiplication factor and parasitic bipolar gain, which are the responsible parameters for the parasitic BJT action, are investigated separately providing a physical explanation. The abnormal subthreshold slope and hysteresis phenomenon are also studied and compared. (C) 2000 Elsevier Science Ltd. All rights reserved.