Showing papers on "Voltage regulator published in 2007"

A Voltage and Frequency Droop Control Method for Parallel Inverters

Abstract: In this paper, a new control method for the parallel operation of inverters operating in an island grid or connected to an infinite bus is described. Frequency and voltage control, including mitigation of voltage harmonics, are achieved without the need for any common control circuitry or communication between inverters. Each inverter supplies a current that is the result of the voltage difference between a reference ac voltage source and the grid voltage across a virtual complex impedance. The reference ac voltage source is synchronized with the grid, with a phase shift, depending on the difference between rated and actual grid frequency. A detailed analysis shows that this approach has a superior behavior compared to existing methods, regarding the mitigation of voltage harmonics, short-circuit behavior and the effectiveness of the frequency and voltage control, as it takes the R to X line impedance ratio into account. Experiments show the behavior of the method for an inverter feeding a highly nonlinear load and during the connection of two parallel inverters in operation.

Full On-Chip CMOS Low-Dropout Voltage Regulator

Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

Abstract: This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

Current regulator for modulating brightness levels of solid state lighting

Abstract: An exemplary embodiment provides a current regulator for controlling variable brightness levels for solid state lighting. The current regulator is couplable to a phase-modulating switch, such as a dimmer switch, which is coupled to an AC line voltage. An exemplary current regulator includes a rectifier; a switching power supply providing a first current; an impedance matching circuit; and a controller. The impedance matching circuit is adapted to provide a second current through the phase-modulating switch when a magnitude of the first current is below a first predetermined threshold, such as a holding current of a triac of the phase-modulating switch. The controller is adapted to determine a root-mean-square (RMS) voltage level provided by the phase-modulating switch from the AC line voltage and to determine a duty cycle for pulse-width current modulation by the switching power supply in response to the comparison of the RMS voltage level to a nominal voltage level.

A Low-Dropout Regulator for SoC With $Q$ -Reduction

Abstract: A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.

Algorithms for Controlling Both the DC Boost and AC Output Voltage of Z-Source Inverter

Abstract: This paper aims to achieve good performance for both the dc boost and the ac output voltage control of the Z-source inverter (ZSI). The algorithm to control linearly the capacitor voltage is suggested in order to improve the transient response for dc boost control of the ZSI. The peak value of the ac output voltage is used to control exactly the ac output voltage to its desired level. A modified space vector pulsewidth modulation scheme is applied to control the shoot-through time for boosting dc voltage. The proposed algorithms are verified with simulation and experiment with a 32-bit digital signal processor.

State-space model of grid-connected inverters under current control mode

Abstract: Growth of distributed generation has led to distribution systems with a mixture of rotating machine generators and inverter interfaced generators. The stability of such networks needs to be studied through the analysis of state-space models, and so suitable models of inverters are needed to complement the well-established models of rotating machines. As machine models include features such as automatic voltage regulators and wash-out functions, the inverter model also includes phase-locking functions and internal control loops. The model for voltage source inverters with an internal current control loop, an outer power regulation loop, a measurement of average power and a phase-locked loop has been developed. The model is presented in detail and is formed with a state-vector, similar to that used for rotating machines. The model includes nonlinear terms but can be linearised about an operating point. The state-space model is verified against a component-level time-step simulation in Simulink/PLECS.

An Ultra-Low-Power Long Range Battery/Passive RFID Tag for UHF and Microwave Bands With a Current Consumption of 700 nA at 1.5 V

Abstract: We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (ie, voltage has dropped below 13 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died When powered by a battery, the current consumption is 700 nA at 15 V (400 nA if internal signals are not brought out on test pads) This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA-hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible The chip is built on a 1-mum digital CMOS process with dual poly layers, EEPROM and Schottky diodes The RF threshold power at 245 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 35 m under FCC unlicensed operation at the 24-GHz microwave band The low threshold is achieved with architectural choices and low-power circuit design techniques At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator Other than the antenna board and a battery, no external components are used

Design and Comparison of High Performance Stationary-Frame Controllers for DVR Implementation

Abstract: The performance of a dynamic voltage restorer (DVR) is determined solely by its controller. The design of high performance control algorithms for DVR control with improved robustness and desirable steady-state and transient characteristics is therefore an important area of study. In this paper, two voltage controllers are proposed in the stationary frame for DVR voltage regulation. A P+resonant controller is first designed to achieve good positive- and negative-sequence fundamental voltage control with the virtue of having high gains around plusmn50Hz. Stationary-to-synchronous frame transformations carried out in traditional synchronous proportional-integral regulators are no longer required with this method. However, with the purpose of achieving explicit robustness in face of parameter variations, an Hinfin controller is also designed. Detailed design procedure is presented to show how an Hinfin controller with high gains around plusmn50Hz can be synthesized through careful selection of its weighting functions. A thorough discussion and performance comparison of these two controllers in both transient and steady-state conditions are also carried out. Finally, both controllers are extensively tested on a laboratory 10-kV medium voltage level DVR system with various voltage sags and loading conditions

Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers

Abstract: This paper introduces a new method for stability analysis and design of fast voltage-loop compensators in rectifiers with power factor correction (PFC). The method has few constraints and can be used with various implementations of the fast voltage loop. It is based on utilization of circle criterion, which unifies frequency domain and nonlinear system analysis. A step-by-step procedure of stability assessment and compensator design is described and demonstrated on two controller implementations. In the first system, the voltage-loop dynamic response of an experimental 200-W digitally-controlled boost-based PFC is improved with a self-tuning comb filter. In the second implementation, it is shown how the circle criterion can be used to design a fast voltage loop for controllers with regulation band, i.e., ldquodead-zone,rdquo element for ripple elimination.

A Dual-Functional Medium Voltage Level DVR to Limit Downstream Fault Currents

Abstract: The dynamic voltage restorer (DVR) is a modern custom power device used in power distribution networks to protect consumers from sudden sags (and swells) in grid voltage. Implemented at medium voltage level, the DVR can be used to protect a group of medium voltage or low voltage consumers. However, the DVR will therefore be tasked to mitigate even more faults involving downstream loads. Large fault currents would flow through the DVR during a downstream fault before the opening of a circuit breaker. This will cause the voltage at point of common coupling (PCC) to drop, which would affect the loads on the other parallel feeders connected to PCC. Furthermore, if not controlled properly, the DVR might also contribute to this PCC voltage sag in the process of compensating the missing voltage, thus further worsening the fault situation. To limit the flow of large line currents, and therefore restore the PCC voltage as well as protect the DVR system components, a downstream fault limiting function is proposed and integrated in the DVR operation. A flux-charge-model feedback algorithm is implemented so that the DVR would act as a large virtual inductance in series with the distribution feeder in fault situations. Controlling the DVR as a virtual inductor would also ensure zero real power absorption during the DVR compensation and thus minimize the stress in the dc link. Finally, the proposed fault current limiting algorithm has been tested in Matlab/Simulink simulation and experimentally on a medium voltage level laboratory DVR system.

A novel voltage-clamped CMOS ISFET sensor interface

Abstract: This paper presents a novel interface for ion-sensitive field effect transistors (ISFET) in which operation at a fixed electrical bias is achieved by voltage clamping. The chosen topology provides pH-dependent current and voltage output signals to drive an appropriate output stage. The circuit can be operated in either strong or weak inversion, depending on the requirements of the application with a pseudo-differential ISFET-REFET topology to allow use of an on-chip reference electrode. Simulation results are shown herein for single-ended and differential implementations. For a single-ended front-end with 1nA bias current, the strong inversion implementation at 2.5V supply has a power consumption of 0.185mW at pH 7 and the weak inversion implementation at 1.5V supply has a power consumption of 13nW at pH 7. The circuit and ISFET-REFET pair have been fabricated in the UMC 0.25mum CMOS technology.

Constant On-Time Regulator With Internal Ripple Generation and Improved Output Voltage Accuracy

Abstract: A buck switching regulator formed on an integrated circuit receives an input voltage and provides a switching output voltage on a switch output node using a constant on-time, variable off-time feedback control loop. The buck switching regulator includes an amplifier comparing a feedback voltage to a reference voltage and generating an output voltage on an output terminal, a first capacitor and a first resistor connected in series between the switch output node and the output terminal of the amplifier, and a second capacitor coupled between the DC output voltage node and the output terminal of the amplifier. The first capacitor and the first resistor generate a ripple voltage signal which is injected onto the output terminal of the amplifier for use in the constant on-time, variable off-time feedback control scheme. The magnitude of the ripple voltage signal is a function of the capacitance value of the second capacitor.

A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors

Abstract: We present a 100MHz eight-phase synchronous buck converter using air-core inductors. The voltage regulator (VR) chip was manufactured in a 90nm CMOS process and mounted on a flip-chip test package together with surface-mount inductors and decoupling capacitors. The measured peak efficiency is 84.0% for Vin/Vout= 2.4V/1.5V and 79.3% for 2.4V/1.2V. The VR delivers a load current of 12A in an area of only 25mm2 and 2.5mm height. This is the first demonstration of a high-frequency VR with air-core inductors, that reaches a record power density of 3.78kW/in3.

Single-Stage AC/DC Converter With Input-Current Dead-Zone Control for Wide Input Voltage Ranges

Abstract: A single-phase single-stage ac/dc converter with input-current dead-zone control is proposed. It is based on flyback topology operating in discontinuous conduction mode (DCM). The current charging into the link capacitor is controlled according to line changes by adjusting the input-current blocking angle to alleviate an excessive increase of the link voltage. The reduced voltage stress can maintain an almost-constant voltage irrespective of load conditions by operating in dc/dc stage in DCM. Experimental results of a 60-W (5-V 12-A output) prototype converter show that the link voltage is limited within 384 V and that the measured power factor is more than 0.91 under universal voltage inputs and entire load conditions. In addition, the maximum efficiency is measured to be about 81% at the rated condition

Current driven memory cells having enhanced current and enhanced current symmetry

Abstract: A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on.

The Effective Role of AVR and PSS in Power Systems: Frequency Response Analysis

Abstract: Two tradeoffs in the effectiveness of automatic voltage regulators (AVRs) and power system stabilizers (PSSs) are investigated together for the first time. The first is the effect of a high-gain fast response AVR on decreasing power system oscillation stability as well as increasing transient stability, and vice versa. The second is that a PSS can reduce transient stability by overriding the voltage signal to the exciter as well as increasing oscillation stability, and vice versa. In essence, the actions of the AVR and PSS devices are dynamically interlinked. A novel Bode frequency response framework for dynamic analysis of AVR and PSS performance and tradeoffs is presented. Bode frequency response also assists with the determination of suitable generator locations for PSSs and the assessment of robustness under changing power system operating conditions.

A Voltage Sag Supporter Utilizing a PWM-Switched Autotransformer

Abstract: This paper proposes a novel distribution-level voltage control scheme that can compensate voltage sag and swell conditions in three-phase power systems. Faults occurring in power distribution systems or facilities in plants generally cause the voltage sag or swell. Sensitivity to voltage sags and swells varies within different applications. For sensitive loads, even a voltage sag of short duration can cause serious problems. Normally, a voltage interruption triggers a protection device, which causes the shutdown of the entire load. In order to mitigate power interruptions, this paper proposes a scheme for voltage sag support based on a pulse width modulated autotransformer. The proposed scheme is able to quickly recognize the voltage sag or swell condition, and it can correct the voltage by either boosting the input voltage during voltage sag events or reducing the voltage during swell events. The key advantage in this voltage control topology is that it uses only one controlled switch per phase to control the output voltage, thereby resulting in minimum cost per kVA. The paper presents the new voltage control topology, as well as the voltage detection method, the snubber design, and the commutation logic for the thyristor bypass switch. Experiments have been carried out to verify the validity of the proposed scheme

Display apparatus, display driving apparatus and method for driving same

Abstract: A light-emitting element capable of emitting light having a preferred gradation level depending on display data. During a precharge period, a data driver applies a precharge voltage to a capacitor via a data line. After the application of the precharge voltage, a voltage converter reads a first reference voltage Vref(t 1 ) and a second reference voltage Vref(t 2 ) to generate a compensation voltage based on a difference between the respective reference voltages. Based on the compensation voltage, a voltage calculator compensates an original gradation level voltage Vorg having a value in accordance with display data generated by a gradation level voltage generator. The voltage calculator generates a compensated gradation level voltage Vpix corresponding to a variation amount of an element characteristic for a transistor Tr 13 for driving light emission to apply the compensated gradation level voltage Vpix to a data line Ld.

Multiobjective Location of Automatic Voltage Regulators in a Radial Distribution Network Using a Micro Genetic Algorithm

Abstract: In rural power systems, the automatic voltage regulators (AVRs) help to reduce energy losses and to improve the energy quality of electric utilities, compensating the voltage drops through distribution lines. In order to help electric companies in the decision-making process, this paper presents a method to define the optimal location of a set of AVRs in electric distribution networks. The optimization process is treated as a multiobjective problem considering the total power losses and the voltage drops in the system as the objectives to be optimized. A novel technique called micro genetic algorithm (muGA) is used to solve the multiobjective problem. This technique is capable of finding, in a very efficient way, the Pareto optimal solutions, giving the decision maker a set of possible (trade-off) solutions from which to choose

Optimization of the Supply Voltage System in Interleaved Converters Using Intercell Transformers

Abstract: Interleaved power converters are now used in many different conversion systems involving various topologies (series or parallel) and related to different fields or loads. This paper deals with interleaved parallel commutation cells using coupling transformers with a possibly high number of cells. The first part of the paper is a reminder of the basics of magnetic couplers addressing monolithic as well as distributed implementations. The limits associated with the conventional supply of such couplers (supply voltages forming a direct polyphase system) are described. In the second part of the paper, an optimized voltage supply improving the performances of the system is introduced. Experimental results obtained on a seven-cells test bench validate the approach

Charge balance control methods for asymmetrical cascade multilevel converters

Abstract: Modulation strategies for multilevel converters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of DC voltage levels. This results in the average current injection and hence the net power drawn from the multiple DC voltages to be unmatched and time varying. Therefore, the DC voltage sources are unregulated, requiring corrective control action to incorporated. In this paper, first a new method is proposed for determination of DC voltage source levels of asymmetric cascade multilevel converters. Then four modulation strategies are proposed for DC power balance realization for asymmetrical multilevel converters expectation of the first unit. All of the expressed theoretical results are confirmed by simulation and experimental results.

A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

Abstract: In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.13- BiCMOS process is presented. The sensor interface consists of a front-end that converts the acceleration signal to voltage, two algorithmic ADCs, two frequency references, and a voltage, current, and temperature reference circuit. Die area and power dissipation are reduced by using time-multiplexed sampling and varying duty cycles down to 0.3%. The chip with a 0.51 active area draws 62 from a 1.8 V supply while sampling temperature at 100 Hz, and four proof masses, each at 1.04 kHz. With a 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 482 , 639 , and 662 , respectively.

Switching voltage regulator with low current trickle mode

Abstract: For load currents greater than a threshold current, the voltage regulator operates in a conventional manner by fully turning on and off one or more switching transistors (16) at a duty cycle necessary to maintain the output voltage a regulated voltage. Upon a load current below a threshold being detected (76), a controller stops the switching of the transistor(s) and applies a reduced drive signal (44) to the high side transistor so as to apply a constant trickle current to the load. Unnecessary components are shut down to save power (42). When the output voltage falls below a threshold (46), the normal switching routine is resumed to recharge the regulator's output capacitor (28) to a certain level, and the regulator once again enters the light load current mode. By not completely shutting down the transistors at light load currents, as in done in a conventional intermittent-operation mode, there is lower power loss by less frequent switching of the transistor(s).

On Load Adaptive Control of Voltage Regulators for Power Managed Loads: Control Schemes to Improve Converter Efficiency and Performance

Abstract: Voltage regulator (VR) efficiency improvement especially at light load currents is important in many applications including those that are battery powered and have energy consumption constraints. However, controlled steady-state and dynamic performance should be maintained while improving efficiency. In this paper, an analytical study of VR losses and voltage ripple deviation is presented and discussed, yielding to proposed control technique, namely "pulse sliding" (PSL) control technique, which results in improved VR conversion efficiency with low and controlled voltage ripple and improved dynamic response. The proposed method and controller achieves the advantages of both variable frequency and fixed frequency controls and eliminates their disadvantages by utilizing information obtained from the inductor peak current, compensation error signal and capacitor current, resulting in an optimum nonlinear switching frequency modulation. PSL is compared to other control methods by both analysis and experiments. Experimental results highly agree with theoretical analysis.

Diode-assisted buck-boost voltage source inverters

Abstract: This paper proposes buck-boost voltage source inverters with a unique X-shape diode-capacitor network inserted between inverter circuitry and dc source for producing a large voltage boost gain. Comparing with other voltage buck-boost techniques, the presented topologies with only a little more passive components can significantly enhance voltage boost capability for dc-ac inversion. With different front-end circuitries, the diode-assisted buck-boost inverters can show different operational principle and voltage boost ratio. Carefully analyzing the operational principle for the inherent energy charging and discharging processes of passive components reveals that the dc-link voltage can alternate between two levels, which therefore demonstrate the phenomena that the specified modulation schemes should note. A modulation scheme that can achieve optimized harmonic switching is first designed with symmetrical state placement in each switching sequence to avoid unnecessary voltage stress across both passive and active components. To reduce the total commutation count, the designed modulation scheme is then modified without increasing voltage stress. All theoretical findings were verified experimentally using a number of scale-down laboratory prototypes.

Microcomputer and microprocessor having flash memory operable from single external power supply

Abstract: A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.

A New Approach to Control DVR Based on Symmetrical Components Estimation

Abstract: The dynamic voltage restorer (DVR) is an effective solution for power quality problems related to voltage. One of the most common control algorithms that are used for the DVR is the symmetrical components method. This paper introduces a new approach for the estimation of the symmetrical components. A modified delta rule structure is proposed and developed which is capable of dealing with multioutput systems for the parameters estimation. An innovative feedforward control, based on the new delta rule structure, is proposed for the series compensator not only to compensate for the zero and negative sequence components, but also to regulate the positive sequence component at the nominal load voltage. One advantage of the proposed control scheme is its insensitivity to parameter variation, a necessity for the series compensator. Experimental verification of the new delta rule algorithm, by using a DSP, is provided. Numerical simulations of the proposed control strategy are conducted to show the robustness, high accuracy, and fast dynamic performance of this novel control algorithm.