Showing papers by "Chenming Hu published in 2018"

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Abstract: Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Abstract: In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper.

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

Abstract: We report on negative capacitance (NC) FinFETs with ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (L CH ) of 450 nm to 30 nm and multiple fin widths (W FIN ) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), D and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same L ch /W Fin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.

Response Speed of Negative Capacitance FinFETs

Abstract: We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.

Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor

Abstract: We propose a new scheme to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials. The scheme is used to extract material parameters from experimental polarization-electric field (P-E) measurements from the literature. A Sentaurus TCAD structure is constructed with the extracted parameters, and the simulated P-E curve is in a good agreement with the experimental data. Furthermore, variation of the device performance in a negative capacitance field-effect transistor (NCFET) due to the spatial distribution of DE and FE phases is studied using Sentaurus TCAD. It is found that the resultant variations of on and off currents can be up to 14.44% and 30.23%, respectively, thus showing the impact of inhomogeneous crystalline phases of the FE material on device performance.

NCFET Design Considering Maximum Interface Electric Field

Abstract: Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$ . Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$ .

A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology

Abstract: We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Abstract: In this work, we use thermal-ALD to prepare ferroelectric HfZrO 2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of I D . Lower thermal budget process, CO 2 far-infrared laser activation and 400°C Ni silicide are employed in the 2-level metal backend integration for maintaining the orthorhombic phase in HZO thin film and minimizing the hysteresis in IV. NC-FinFET inverter has 77% higher voltage gain compared to FinFET-inverter employing HfO 2 gate dielectric. NC-FinFET ring oscillator exhibit small speed and power advantages over FinFET oscillator. For the first time, NC-FET cut-off frequency (F t ) frequency is measured, 23.1 GHz or 23% higher than the control FET Ft. NC-FinFET SRAM was observed to exhibit large noise margin.

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

Abstract: Negative capacitance field effect transistor (NCFET) is designed in 5-nm FinFET node, which simultaneously meets the low-power and high-performance targets of ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ at ${V}_{\sf dd}= 0.5$ V and ${V}_{\sf dd}= 0.23$ V, respectively, while the international roadmap for devices and systems (ITRS 2.0) projected ${V}_{\sf dd}$ is 0.65 V for both. The impact of power supply and parasitic capacitance on the performance of NCFET is studied. It is demonstrated that NCFET can be designed for fluid subthreshold swing (SS) behavior such that SS is degraded around ${V}_{\sf gs}=0$ , ${V}_{\sf ds}={V}_{\sf dd}$ , and is improved in the subthreshold region. This helps in combating OFF-current variation due to the threshold voltage fluctuations. A compact model to determine such design conditions is presented. Parasitic capacitance and the ferroelectric material parameters should be cooptimized for the target ${V}_{\sf dd}$ .

In 0.53 Ga 0.47 As FinFET and GAA-FET With Remote-Plasma Treatment

Abstract: This letter presents a remote NH3/N2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current ( ${I}_{\textsf {DS}}$ ), transconductance ( ${G}_{m}$ ), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized.

First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf 0.5 Zr 0.5 O 2 Ferroelectric Gate Stack

Abstract: We demonstrate, for the first time, the negative capacitance (NC) In 0.53 Ga 0.47 As nMOSFET with 8-nm Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al 2 O 3 /InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).

Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

Abstract: A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing ( $385\ \mu \mathrm{A}/\mu \mathrm{m}$ ), and high I on /I off (>106). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition

Abstract: We model the effects of cross-sectional radius scaling on ${C}$ – ${V}$ and ${I}$ – ${V}$ characteristics of gate-all-around FETs (GAAFETs), capturing the continuous transition from a 3-D electron system to a 1-D electron system. We have obtained computationally efficient models for effective mass, bandgap, and subband energies as functions of the cross-sectional radius and gate voltage based on simple approximate analytic expressions. Together, they provide a compact model for VLSI circuit simulation, especially for analog and RF circuits that will be seriously affected by the new humps and peaks in ${C}$ – ${V}$ and ${I}$ – ${V}$ introduced by the subbands. The model has been validated with ${k}\cdot {p}$ -based technology computer aided design simulations as well as measured data. To the best of our knowledge, this is the first compact model capturing cross-sectional size-dependent dimensional crossover (3-D to 1-D) in ${I}$ – ${V}$ and ${C}$ – ${V}$ for GAAFETs.

Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability

Abstract: A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented. The study considers the random variation of ferroelectric remnant polarization $(\boldsymbol{P_{r}})$ and the presence of dielectric phases. In order to keep the ferroelectric-film induced device variability less than those induced by other sources (RDF, GER, FER, and MGG), we found that the DE content must be less than 20%, which is theoretically possible, and the grain to grain $\boldsymbol{P_{r}}$ variations less than 27%. While uniform single-crystalline ferroelectric film would provide the least device variation, we found 4 nm grains to produce less device variability than 5.3 nm grains due to the larger number of grains in the channel area.

Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs

Abstract: We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

Modeling of Advanced RF Bulk FinFETs

Abstract: The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.

Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation

Abstract: A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. A 2D Numerical Simulation for FinFETs coupled with the Landau’s Ferroelectric Model captures device characteristics. A new version of the distributed Negative-Capacitance FinFET Compact Model is also presented in this work, where influence of short-channel effects in Ferroelectric voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, is presented for the gate voltage amplification of Negative Capacitance FinFETs in ring-oscillator circuits.

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs

Abstract: Anomalous transconductance with nonmono- tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.

A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect

Abstract: A physics-based unified flicker noise model for FDSOI transistor is proposed. Flicker noise power spectral density (PSD) at the front and back interfaces are calculated using oxide-trap-induced carrier number (CNF) and correlated surface mobility fluctuation (CMF) mechanisms. The model predicts correct flicker noise behavior from weak inversion region to strong inversion region for a wide range of the front and backgate voltages. The proposed model is computationally efficient and implementable in any SPICE model for circuit simulations.

Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET

Abstract: We present a charge-based compact model for induced gate thermal noise for a fully depleted silicon-on-insulator transistor. The model uses front- and back-gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simulations. The model predicts the high-frequency behavior with good accuracy while capturing the back-bias dependence.

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation

Abstract: This work examines the metal-ferroelectric-insulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse $V_{ds}$-dependency of threshold voltage $(V_{T})$, also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low $V_{DD}$.

UTBSOI MOSFET with corner spacers for energy-efficient applications

Abstract: Parasitic capacitance is a critical challenge in improving the device and circuit performance in nanoscale devices like the UTBSOI MOSFET and FinFET. Scaling the contact pitch decreases the separation between the gate and the source/drain contacts which increases the contribution of parasitic capacitance to the total capacitance as the devices are scaled. According to ITRS 2.0, the parasitic capacitance should be limited to be less than 60% of the total capacitance [1]. For sub- 20 nm node devices, introduction of source/drain underlaps improves the short-channel performance [2]. The additional resistance due to underlaps can be reduced by the introduction of higher-K spacers [3,4], and dual-K spacers trading-off parasitic capacitance [5-7]. On the other end, since air or vacuum has a dielectric constant of 1, vacuum or air-gap spacers can reduce the parasitic capacitance [8-12]. In underlapped nanoscale devices, corner spacer design in which a higher-K oxide is present only in the bottom corner of the gate and the rest of the spacer consists of a lower-K dielectric will be required to simultaneously reduce underlap resistance and parasitic capacitance [13-15]. Fig. 1 shows the different spacer design options explored such as the full spacer, dual-K spacer and corner spacer. The full spacer has a single dielectric material. The dual-K spacer has an inner higher-K and an outer lower-K dielectric. The corner spacer has a higher-K dielectric present only at the bottom corner of the gate and the rest of the spacer region is made up of a lower-K dielectric. The impact of corner spacer design on UTBSOI MOSFET has not been studied. In this paper, using TCAD simulations, we design and optimize corner spacer for UTBSOI MOSFET for the 11/10 nm node.

Semiconductor device with silicided source/drain region

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Unified compact model for gate all around fets-nanosheets, nanowires, multi bridge channel MOSFETs

Abstract: A unified compact model for gate-all-around (GAA) FETs is discussed. This single unified model can accurately model different shapes of GAA FETs. In this work, we present its validation with the reported GAA FETs: stacked GAA nanosheet, stacked nanowire MOSFETs, Multi-bridge-channel MOSFETs and Twin silicon nanowire MOSFETs. This study shows that the BSIM-CMG unified multi-gate MOSFET model is ready for production design of silicon GAA based circuits and technology-product co-development for future technology nodes.