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Jong-Ho Lee

Researcher at Seoul National University

Publications -  1054
Citations -  14204

Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.

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Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics

TL;DR: In this paper, a repeatable process of forming uniform, small-size and high-density Si quantum dots on oxide-nitride tunneling dielectrics was developed and an EEPROM which showed room temperature single electron effects.
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Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme.

TL;DR: A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture and the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight.
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Effect of leptin on differentiation of human dental stem cells

TL;DR: Evidence is provided that leptin acts as an important modulator of dental MSCs differentiation and had a relatively stronger promoting effect on cemento/odontoblastic differentiation and a suppressing effect on adipogenesis in PDLSCs than in DPSCs.
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Facet evolution in selective epitaxial growth of Si by cold-wall ultrahigh vacuum chemical vapor deposition

TL;DR: In this article, a model to explain the effect of growth temperature on the facet morphology in terms of the surface mass transport and mass accumulation processes on facet surfaces is proposed, and the stability of the (211) plane is also discussed.
Proceedings ArticleDOI

High-Density and Highly-Reliable Binary Neural Networks Using NAND Flash Memory Cells as Synaptic Devices

TL;DR: The large on/off current ratio of NAND flash cells can implement high-density and highly-reliable BNNs without error correction codes and it is shown that without conventional ISPP scheme, only 1 erase or program pulse can achieve sufficiently low bit-error rate.