J
Jong-Ho Lee
Researcher at Seoul National University
Publications - 1054
Citations - 14204
Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.
Papers
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Journal ArticleDOI
Biomechanical Evaluation of Magnesium-Based Resorbable Metallic Screw System in a Bilateral Sagittal Split Ramus Osteotomy Model Using Three-Dimensional Finite Element Analysis
TL;DR: The Mg-based resorbable screw system is a promising alternative to the IN-based system and its biomechanical stability is compared with those of titanium (Ti)-based and polymer (IN)-based systems.
Proceedings ArticleDOI
Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics
Seok Joo Doh,Hyung-Suk Jung,Yunseok Kim,Hajin Lim,Jong Pyo Kim,Jung Hyoung Lee,Jong-Ho Lee,Nae-In Lee,Ho-Kyu Kan,Kwang-Pyuk Suh,Seong Geon Park,Sang Bom Kang,Gil Heyun Choi,Youngsu Chung,Hion-Suck Baikz,Hdyo-Sik Chang,Mann Ho Cho,Dae Won Moon,Hong-bae Park,Moonju Cho,Cheol Seong Hwang +20 more
TL;DR: In this article, the effect of ozone pre-treatment on bias temperature instability (BTI) and electrical properties of high-k gate dielectrics was investigated, and it was shown that O/sub 3/pre-treatment effectively suppresses the incorporation of impurities (such as nitrogen (N), hydrogen (H), and water related species), resulting in the improvement of NBTI characteristics.
Proceedings ArticleDOI
Characterization of traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT
Jong-Ho Bae,In-jun Hwang,Jongmin Shin,Hyuck-In Kwon,Chan Hyeong Park,Jong-Bong Ha,Jaewon Lee,Hyoji Choi,Jongseob Kim,Jong-Bong Park,Jae-joon Oh,Jai-Kwang Shin,U-In Chung,Jong-Ho Lee +13 more
TL;DR: In this article, trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT with SiO 2 gate dielectric were characterized.
Proceedings ArticleDOI
A study of ESD-induced latent damage in CMOS integrated circuits
Yoonjong Huh,M.G. Lee,Jong-Ho Lee,H.C. Jung,Tong Li,D.H. Song,Y.J. Lee,J.M. Hwang,Y.K. Sung,Sung-Mo Kang +9 more
TL;DR: In this paper, the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes and the impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.
Patent
Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices
TL;DR: In this article, high dielectric layers formed from layers of hafnium oxide, zirconium oxide or aluminum oxide, yttrium oxide, and other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrate were treated by oxidation, annealing, or a combination of oxidation and anneal to form high dieelastic layers having superior mobility and interfacial characteristics.