J
Jong-Ho Lee
Researcher at Seoul National University
Publications - 1054
Citations - 14204
Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.
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Elimination of the gate and drain bias stresses in I–V characteristics of WSe2 FETs by using dual channel pulse measurement
TL;DR: In this paper, the authors used the dual channel pulsed I-V measurement with a short turn-on time (10−4) and a long turn-off time (1
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Pulsed I –V measurement method to obtain hysteresis-free characteristics of graphene FETs
TL;DR: In this article, the current-voltage (I-V) characteristics of the graphene field effect transistors (GFETs) are measured by the dc, fast I-V (FIV), and pulsed I-v (PIV) methods and analyzed.
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Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
Heesang Kim,Byoungchan Oh,Kyungdo Kim,Seon-Yong Cha,Jae-Goan Jeong,Sung-Joo Hong,Jong-Ho Lee,Byung-Gook Park,Hyungcheol Shin +8 more
TL;DR: In this article, a trap inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain.
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Synaptic device using a floating fin-body MOSFET with memory functionality for neural network
Sung Yun Woo,Kyu-Bong Choi,Suhwan Lim,Sung-Tae Lee,Chul-Heung Kim,Won-Mook Kang,Dongseok Kwon,Jong-Ho Bae,Byung-Gook Park,Jong-Ho Lee +9 more
TL;DR: In pattern recognition for 28 × 28 MNIST handwritten patterns, high learning performance with a classification accuracy of 95.74% is obtained when the unidirectional weight update method (B) is used.
Journal Article
Design Consideration of Body-Tied FinFETs (Ω MOSFETs) Implemented on Bulk Si Wafers
TL;DR: In this article, the body-tied FinFETs (bulk fin-fets) implemented on bulk Si substrate were characterized through 3-dimensional device simulation.