抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Infectious Diseases Society of America.

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Transparent electronics is today one of the most advanced topics for a wide range of device applications. The key components are wide bandgap semiconductors, where oxides of different origins play an important role, not only as passive component but also as active component, similar to what is observed in conventional semiconductors like silicon. Transparent electronics has gained special attention during the last few years and is today established as one of the most promising technologies for leading the next generation of flat panel display due to its excellent electronic performance. In this paper the recent progress in n- and p-type oxide based thin-film transistors (TFT) is reviewed, with special emphasis on solution-processed and p-type, and the major milestones already achieved with this emerging and very promising technology are summarizeed. After a short introduction where the main advantages of these semiconductors are presented, as well as the industry expectations, the beautiful history of TFTs is revisited, including the main landmarks in the last 80 years, finishing by referring to some papers that have played an important role in shaping transparent electronics. Then, an overview is presented of state of the art n-type TFTs processed by physical vapour deposition methods, and finally one of the most exciting, promising, and low cost but powerful technologies is discussed: solution-processed oxide TFTs. Moreover, a more detailed focus analysis will be given concerning p-type oxide TFTs, mainly centred on two of the most promising semiconductor candidates: copper oxide and tin oxide. The most recent data related to the production of complementary metal oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also be presented. The last topic of this review is devoted to some emerging applications, finalizing with the main conclusions. Related work that originated at CENIMAT|I3N during the last six years is included in more detail, which has led to the fabrication of high performance n- and p-type oxide transistors as well as the fabrication of CMOS devices with and on paper.

Oxide Semiconductor Thin‐Film Transistors: A Review of Recent Advances

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

In this work, highly scalable charge trap flash (CTF) memory with bandgap-engineered storage node and vertical channel is proposed. Due to the compact cell layout without individual junction contacts, NAND flash memory has the most suitable architecture for mobile data storage media. In other to achieve even higher integration density, two NAND flash memory cells in the conventional sting are put together to have a common vertical channel as shown in Fig. 1(a). The biggest merit in this array feature is that half-level reduction in footprint can be achieved by using the sidewall control gates as shown in Fig. 1(b). Due to the vertical channel, the channel length can be simply controlled by anisotropic dry etch, which suppresses short channel effects (SCEs) effectively and enlarges the sensing margin. Fig. 1(c) shows the schematic view of the array with circuit symbols. Also, in this novel flash memory, the memory storage node uses a bandgap-engineered (BE) multi-layer, where the oxide-nitride-oxide triple-layer replaces the tunnel oxide to improve the performances in operations [1–3]. The process architecture for fabricating the vertical BE-NAND flash memory is summarized in Fig. 2. The fin structures in both bitline (BL) and wordline (WL) directions have been formed by sidewall spacer patterning [4]. Among the several possible combinations of materials [5–6], nitride (Si 3 N 4 ) and TEOS are used for the sidewall spacer and the supporting dummy pattern, respectively. Fig. 3 and 4 shows the process flow for Si fin constructions in both directions. After the fin consisted of Si-STI alternating pillars is formed in the WL direction, ONONO (20/20/20/60/60 A) multi-layer is deposited. All the oxide layers were deposited by medium temperature oxidation (MTO) in an ambient of N 2 160 sccm and DCS 40 sccm. The tunneling and storage nitride layers were deposited by LPCVD in the ambient of NH 3 30 sccm/DCS 10 sccm/750 °C and NH 3 100 sccm/DCS 30 sccm/785 °C, respectively. Subsequently, physically separated sidewall control gates used as WLs are formed by etch-back process. Fig. 5(a) through (c) show the images for fin structures and top view of the vertical BE-NAND flash with independent sidewall gates. After ILD/CMP/metallization/alloy, the fabrication is completed.

Highly scalable vertical bandgap-engineered NAND flash memory

Young-Min Shin, Hun-Jong Chung, Kang-Min Ahn, Hee-Jung Park, Mi-Ae Sung, Soung-Min Kim, Soon-Jung Hwang, Myung-Jin Kim, Jeong-Won Jahng, Sung-Po Kim, Eun-Kyung Yang, Kye-Yong Song, Jong-Ho Lee Department of Oral and Maxillofacial Surgery, Graduate School of Dentistry, Seoul National University & Dental Research Institute 2 Department of Pediatrics, Chung-Ju Medical Hospital, Kon-Kuk University 3 Department of Oral and Maxillofacial surgery, School of Dentistry, Kangnung National University Department of Pharmacology, Yonsei Medical University Bioland R&D center, Department of Pathology, Medical School, Chungang University

Fabrication of myomucosal flap using cultured oral epithelium in rabbit model

In order to develop strategies for minimizing deposition of contaminant particles of diameters ranging from 0.1 to 1.0 μm on a wafer, the effect of thermophoresis on a particle deposition velocity was numerically studied. The angle between wafer surface and direction of free-stream flow was introduced as a system parameter. Convection, diffusion, sedimentation, and thermophoresis were included as particle transport mechanisms. Similarity transform was applied to the model equations and obtained equations with dimensions reduced by one. The results suggest that it is possible to enhance the removal of particles of diameter ranging from 0.1 to 1.0 μm by heating with a temperature difference of 10–30°C between wafer surface and the air stream. If the filter of a clean room removes well around 0.1 μm sized particles, the free-slream velocity or flow angle should be increased for the effective removal of particle by thermophoresis, but, if the filter is efficient in removing particles around 1 μm, the free-stream velocity or flow angle should be decreased.

Numerical simulation of thermophoretic particle decontamination in clean rooms

Formation of basement membrane and stratification of Rabbit oral keratinocytes cultured on human acellular dermal matrix

For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.

Jong-Ho Lee

Papers

Highly scalable vertical bandgap-engineered NAND flash memory

Fabrication of myomucosal flap using cultured oral epithelium in rabbit model

Numerical simulation of thermophoretic particle decontamination in clean rooms

Formation of basement membrane and stratification of Rabbit oral keratinocytes cultured on human acellular dermal matrix

Poly-silicon quantum-dot single-electron transistors