J
Jong-Ho Lee
Researcher at Seoul National University
Publications - 1054
Citations - 14204
Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.
Papers
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Journal ArticleDOI
Local-Degradation-Induced Threshold Voltage Shift in Turned-OFF Amorphous InGaZnO Thin Film Transistors Under AC Drain Bias Stress
Jong-In Kim,In-Tak Cho,Chan-Yong Jeong,Daeun Lee,Hyuck-In Kwon,Keum Dong Jung,Mun Soo Park,Mi Seon Seo,Kim Tae Young,Je-Hun Lee,Jong-Ho Lee +10 more
TL;DR: In this article, the instability of turned-off a-IGZO TFTs under dc $V_{\mathrm {\mathbf {DS}}}$ stressing was investigated, and the negative threshold voltage shift was accelerated with increasing duty cycle despite the same effective stress time.
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Reliability of bottom-gate graphene field-effect transistors prepared by using inductively coupled plasma-chemical vapor deposition
TL;DR: In this article, a stretched-exponential time dependence model based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics is applied in fitting the time dependence of the transfer curve shifts in all stress conditions.
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Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications
Jong-Ho Bae,Jong-Won Back,Min-Woo Kwon,Jae Hwa Seo,Keon Yoo,Sung Yun Woo,Kyungchul Park,Byung-Gook Park,Jong-Ho Lee +8 more
TL;DR: A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell as discussed by the authors.
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Fabrication and characteristics of P-channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure
Il Hwan Cho,Tai-su Park,Jeong Dong Choe,Hye-Jin Cho,Donggun Park,Hyungcheol Shin,Byung-Gook Park,Jong Duk Lee,Jong-Ho Lee +8 more
TL;DR: A p-channel silicon-oxide-nitrideoxide-silicon (SONOS) flash memory device based on bulk fin shaped field effect transistor (FinFET) structure was fabricated and characterized as a highly scalable device structure as discussed by the authors.
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Novel Double-Gate 1T-DRAM Cell Using Nonvolatile Memory Functionality for High-Performance and Highly Scalable Embedded DRAMs
TL;DR: In this paper, a double-gate 1T-DRAM cell with nonvolatile memory (NVM) functionality was proposed for sub-80-nm DRAM technology that has a siliconoxide-nitride-oxide-silicon type storage node on the back gate (control gate).