抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Infectious Diseases Society of America.

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Transparent electronics is today one of the most advanced topics for a wide range of device applications. The key components are wide bandgap semiconductors, where oxides of different origins play an important role, not only as passive component but also as active component, similar to what is observed in conventional semiconductors like silicon. Transparent electronics has gained special attention during the last few years and is today established as one of the most promising technologies for leading the next generation of flat panel display due to its excellent electronic performance. In this paper the recent progress in n- and p-type oxide based thin-film transistors (TFT) is reviewed, with special emphasis on solution-processed and p-type, and the major milestones already achieved with this emerging and very promising technology are summarizeed. After a short introduction where the main advantages of these semiconductors are presented, as well as the industry expectations, the beautiful history of TFTs is revisited, including the main landmarks in the last 80 years, finishing by referring to some papers that have played an important role in shaping transparent electronics. Then, an overview is presented of state of the art n-type TFTs processed by physical vapour deposition methods, and finally one of the most exciting, promising, and low cost but powerful technologies is discussed: solution-processed oxide TFTs. Moreover, a more detailed focus analysis will be given concerning p-type oxide TFTs, mainly centred on two of the most promising semiconductor candidates: copper oxide and tin oxide. The most recent data related to the production of complementary metal oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also be presented. The last topic of this review is devoted to some emerging applications, finalizing with the main conclusions. Related work that originated at CENIMAT|I3N during the last six years is included in more detail, which has led to the fabrication of high performance n- and p-type oxide transistors as well as the fabrication of CMOS devices with and on paper.

Oxide Semiconductor Thin‐Film Transistors: A Review of Recent Advances

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Off-state leakage currents of MOSFETs with high-κ dielectrics

This work demonstrates design and performances of core-shell dual-gate nanowire synaptic transistor with short/long term plasticity. The novel structure helps equip better capacitive coupling between dual gates through full depletion of carriers from the Si channel and construct deeper potential well for charge storage, which eventually increases the probability for short-term-to-long-term memory transition by reducing the recombination. The dual-gate operation effectively realizes the short-and the long-term potentiation in the proposed device for hardware-driven neuromorphic system.

Core-Shell Dual-Gate Nanowire Synaptic Transistor with Short/Long-Term Plasticity

We propose for the first time a method for erasing one selected cell in Vertical NAND (VNAND) flash memory. By controlling the voltage applied to the terminals (switch devices and cells) of the VNAND string array, 1-bit erase (GIDL generation) of one selected cell and erase inhibition (GIDL suppression) of unselected cells are successfully verified. Compared to the existing method, the 1-bit erase method reduces the current fluctuation by 17 times at an IBL of 50 nA and reduces the Vth dispersion of >2 V to ~0.2 V or less.

First Demonstration of 1-bit Erase in Vertical NAND Flash Memory

Cross-facial nerve graft is considered the treatment of choice for facial reanimation in patients with unilateral facial palsy caused by central facial nerve damage. In most cases, a traditional parotidectomy skin incision is used to locate the buccal and zygomatic branches of the facial nerve. In this study, cross-facial nerve graft with the sural nerve was planned for three patients with facial palsy through an intraoral approach. An incision was made on the buccal cheek mucosa, and the dissection was performed to locate the buccal branch of the facial nerve. The parotid papillae and parotid duct were used as anatomic landmarks to locate the buccal branch. The intraoral approach is more advantageous than the conventional extraoral approach because of clear anatomic marker (parotid papilla), invisible postoperative scar, reduced tissue damage from dissection, and reduced operating time.

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Per-oral cross-facial sural nerve graft for facial reanimation

This paper investigates gate-induced drain leakage (GIDL) characteristics in a cell string consisting of gated-diode memory cells. Gated-diode cells have an oxide/ nitride/oxide gate dielectric stack to implement a nonvolatile memory and are formed in a cell string with a select MOSFET located at one end. Gated diodes in a string are investigated with regard to memory performance. The string current is the sum of individual GIDL currents from the cells. It can be accurately controlled by programming or erasing the cells. Using a $1\times 6$ cell string, a 6-b binary-weighted current-steering digital-to-analog converter (DAC) is demonstrated experimentally. By programming the cells to have binary-weighted cell currents by means of an incremental step pulse programming, the effective number of bits becomes 5.98 b in the DAC. As a means of increasing the GIDL current, a thin SiGe epilayer is adopted, with a simulated current improvement of more than $10^{3}$ times at a gate voltage of −3 V.

Jong-Ho Lee

Papers

Off-state leakage currents of MOSFETs with high-κ dielectrics

Core-Shell Dual-Gate Nanowire Synaptic Transistor with Short/Long-Term Plasticity

First Demonstration of 1-bit Erase in Vertical NAND Flash Memory

Per-oral cross-facial sural nerve graft for facial reanimation

GIDL Characteristics in Gated-Diode Memory String and Its Application to Current-Steering Digital-to-Analog Conversion