J
Jong-Ho Lee
Researcher at Seoul National University
Publications - 1054
Citations - 14204
Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.
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Analyzing the factors that influence occult metastasis in oral tongue cancer.
TL;DR: The analysis of these clinico-histopathological and immunohistochemical factors can help to determine neck dissection in clinically negative (cN0) patients.
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Blip up‐down acquisition for spin‐ and gradient‐echo imaging (BUDA‐SAGE) with self‐supervised denoising enables efficient T2, T2*, para‐ and dia‐magnetic susceptibility mapping
Zijing Zhang,Jaejin Cho,Long Wang,Congyu Liao,Hyeong-Geol Shin,Xiaozhi Cao,Jong-Ho Lee,Jinmin Xu,Tao Zhang,Huihui Ye,Kawin Setsompop,Haifeng Liu,Berkin Bilgic +12 more
TL;DR: In vivo results demonstrate the ability of BUDA-SAGE to provide whole-brain, distortion-free, high-resolution, multi-contrast images and quantitative T2 /T2 * maps, as well as yielding para- and dia-magnetic susceptibility maps.
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A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure
Myoung-Sun Lee,Sung-Min Joe,Jang-Gn Yun,Hyungcheol Shin,Byung-Gook Park,Sangsik Park,Jong-Ho Lee +6 more
TL;DR: The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NANDflash memory with planar structure were investigated.
Journal ArticleDOI
Flash Memory Device with `I' Shape Floating Gate for Sub-70 nm NAND Flash Memory
Sang-Goo Jung,Jong-Ho Lee +1 more
TL;DR: In this article, the authors proposed a novel I shape floating gate applicable to the sub-70 nm flash memory cell with high performance and scalability, which has modified floating gate of conventional flash memory to have high coupling-ratio (CR), low effect of interference or cross-talk.