J
Jong-Ho Lee
Researcher at Seoul National University
Publications - 1054
Citations - 14204
Jong-Ho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Field-effect transistor & Threshold voltage. The author has an hindex of 45, co-authored 928 publications receiving 11335 citations. Previous affiliations of Jong-Ho Lee include Massachusetts Institute of Technology & Kyungpook National University.
Papers
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Journal ArticleDOI
Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String
Sung-Min Joe,Jeong-Hyong Yi,Sung-Kye Park,Hyungcheol Shin,Byung-Gook Park,Young June Park,Jong-Ho Lee +6 more
TL;DR: In this paper, the effect of random telegraph noise on threshold voltage fluctuation (ΔVth) was analyzed with program/erase mode of a cell and pass cells in a string.
Journal ArticleDOI
On-Chip Training Spiking Neural Networks Using Approximated Backpropagation With Analog Synaptic Devices.
Dongseok Kwon,Suhwan Lim,Jong-Ho Bae,Sung-Tae Lee,Hyeongsu Kim,Young-Tak Seo,Seongbin Oh,Jangsaeng Kim,Kyuho Yeom,Byung-Gook Park,Jong-Ho Lee +10 more
TL;DR: An efficient on-chip training scheme approximating backpropagation algorithm suitable for hardware implementation of hardware-based spiking neural networks is proposed and it is shown that the accuracy of the proposed scheme for SNNs is close to that of conventional artificial neural networks (ANNs) by using the stochastic characteristics of neurons.
Journal ArticleDOI
Modelling of the nanoscale channel length effect on the subthreshold characteristics of junctionless field-effect transistors with a symmetric double-gate structure
TL;DR: In this article, an analytical sub-threshold current of deep nanoscale short channel junctionless field effect transistors (JL FETs) with a symmetric double-gate (DG) structure has been derived from two-dimensional Poisson's equation using a variable separation technique.
Proceedings ArticleDOI
PMOS body-tied FinFET (Omega MOSFET) characteristics
Tai-su Park,D. Park,Ju-hyuck Chung,Eun-Jung Yoon,Shi-Eun Kim,H.-J. Cho,J.-D. Choe,Jong-Chul Choi,B.M. Yoon,Jung-Im Han,Bohyun Kim,S. Choi,Kyungryun Kim,E. Yoon,Jong-Ho Lee +14 more
TL;DR: In this paper, the authors introduced PMOS body-tied FinFet characteristics for the 1/spl mu/m/m design and the /spl Omega/ MOSFET, which has lower DIBL characteristics than conventional PMOS transistor.
Proceedings ArticleDOI
A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control
Hyung-Suk Jung,Jong-Ho Lee,Sung Kee Han,Yunseok Kim,Ha Jin Lim,Min-Joo Kim,Seok Joo Doh,Mi Young Yu,Nae-In Lee,Hye-Lan Lee,Taek-Soo Jeon,Hag-Ju Cho,Sang Bom Kang,Sang-Yong Kim,Im Soo Park,Dong Chan Kim,Hionsuck Baik,Young Su Chung +17 more
TL;DR: In this paper, a technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS gates is demonstrated.