scispace - formally typeset
Proceedings ArticleDOI

Fabrication of high Ge content SiGe layer on Si by Ge condensation technique

TLDR
In this article, the accumulation and diffusion mechanism is found to be dependent on the thermal environment, and SiGe layers with high Ge content with proper interface is also achieved for the first time and presented in this article.
Abstract
It is known that Ge condensation is achieved by thermal oxidation of the SiGe layer whereby Si oxidizes faster as compared to Ge, and the Ge atoms are rejected from the oxide into the SiGe layer below. As the Ge diffusion and accumulation varies with gas flow and temperature, detailed investigations are carried out and process conditions are optimized in this work. The accumulation and diffusion mechanism is found to be dependent on the thermal environment. Further to that, SiGe layers with high Ge content with proper interface is also achieved for the first time and presented in this article. SiGe on bulk Si with 30% and above 50% Ge content are fabricated using this technique for the first time

read more

Citations
More filters
Patent

Germanium FinFETs having dielectric punch-through stoppers

TL;DR: In this paper, a method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk Silicon substrate.
Patent

Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights

TL;DR: In this article, a first Fin field effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first height different from the first fin height.
Patent

Two-dimensional condensation for uniaxially strained semiconductor fins

TL;DR: In this paper, techniques for enabling multi-sided condensation of semiconductor fin-based transistors are described, where a fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion.
Patent

FinFETs having dielectric punch-through stoppers

TL;DR: In this paper, a planar transistor on a first portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor, where the fin is electrically isolated from the substrate by an insulator.
Patent

Antifuse element utilizing non-planar topology

TL;DR: In this article, techniques for providing non-volatile antifuse memory elements and other antifusor links are disclosed, where the antifouse memory elements are configured with non-planar topology such as FinFET topology.
References
More filters
Journal ArticleDOI

Relaxed GexSi1−x structures for III–V integration with Si and high mobility two‐dimensional electron gases in Si

TL;DR: In this article, a large lattice constant on Si has been obtained by growing compositionally graded GexSi1−x on Si, and these buffer layers have been characterized with electron-beam-induced current, transmission electron microscopy and x-ray diffraction to determine the extent of relaxation, threading dislocation density, the surface morphology, and the optical properties.
Journal ArticleDOI

Si/SiGe heterostructures: from material and physics to devices and circuits

TL;DR: In this paper, the authors present a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system, in particular, the important device technologies in mainstream microelectronics.
Journal ArticleDOI

Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique

TL;DR: In this paper, a strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors, which exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface.
Journal ArticleDOI

A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs

TL;DR: In this article, a novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs).
Journal ArticleDOI

Crosshatching on a SiGe film grown on a Si(001) substrate studied by Raman mapping and atomic force microscopy

TL;DR: The morphology, stress, and composition distributions of the crosshatch pattern on a SiGe film grown on a substrate using a low-temperature Si buffer are studied by atomic force and Raman microscopies.
Related Papers (5)