Journal ArticleDOI
Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique
TLDR
In this paper, a strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors, which exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface.Abstract:
A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...read more
Citations
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Journal ArticleDOI
Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Journal ArticleDOI
High-k/Ge MOSFETs for future nanoelectronics
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
Journal ArticleDOI
Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance
Shinichi Takagi,T. Iisawa,Tsutomu Tezuka,T. Numata,Shu Nakaharai,N. Hirashita,Yoshihiko Moriyama,Koji Usuda,Eiji Toyoda,Sanjeewa Dissanayake,Masato Shichijo,Ryosho Nakane,Satoshi Sugahara,Mitsuru Takenaka,Naoharu Sugiyama +14 more
TL;DR: In this article, the authors reviewed the recent approaches in realizing carrier-transport-enhanced CMOS, and the critical issues, fabrication techniques, and device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented.
Journal ArticleDOI
Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping
TL;DR: In this article, a defect-free germanium was demonstrated in SiO2 trenches on silicon via aspect ratio trapping, whereby defects arising from lattice mismatch are trapped by laterally confining sidewalls.
Journal ArticleDOI
Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials
Marc Heyns,Wilman Tsai +1 more
TL;DR: In this paper, the International Technology Roadmap for Semiconductors (ITRS) indicates the requirements and technological challenges in the microelectronics industry in various technology nodes, and the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices are given in this issue of MRS Bulletin.
References
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Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI
Measurements of alloy composition and strain in thin GexSi1−x layers
TL;DR: In this paper, the utility of Raman spectroscopy for the simultaneous determination of composition and strain in thin GexSi1−x layers has been investigated using data from the literature and new data for the strain shift of the SiSi phonon mode presented here.
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Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction
TL;DR: In this article, a promising fabrication method for a Si1−xGex-on-insulator (SGOI) virtual substrate and evaluation of strain in the Si layer on this SGOI substrate are presented.
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A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs
TL;DR: In this article, a novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs).
Journal ArticleDOI
Ultrahigh room-temperature hole Hall and effective mobility in Si0.3Ge0.7/Ge/Si0.3Ge0.7 heterostructures
TL;DR: In this paper, the authors obtained ultrahigh room-temperature (RT) hole Hall and effective mobility in Si0.3Ge0.7 heterostructures with very small parallel conduction.