Proceedings ArticleDOI
HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector
TLDR
In this paper, a double-layer stacked HfOx vertical RRAM is demonstrated for 3D crosspoint architecture using a cost-effective fabrication process, and a unique write/read scheme is proposed for 3d cross-point architecture.Abstract:
Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current ( 108 cycles), half-selected read disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture. Analysis shows that for such 3D selector-less array, a large R on (∼100kΩ) from the non-linear I-V helps reduce the sneak path current, and a low interconnect resistance using metal planes as word lines reduces the undesirable voltage drop on the interconnect. As a conservative estimate, simulation shows that Mb-scale array without cell selector is achievable.read more
Citations
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Journal ArticleDOI
The future of electronics based on memristive systems
TL;DR: The state of the art in memristor-based electronics is evaluated and the future development of such devices in on-chip memory, biologically inspired computing and general-purpose in-memory computing is explored.
Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Journal ArticleDOI
Emerging Memory Technologies: Recent Trends and Prospects
Shimeng Yu,Pai-Yu Chen +1 more
TL;DR: This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change randomAccess memory (PCRAM), and resistive random accessMemory (RRAM).
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Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
References
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Journal ArticleDOI
Metal–Oxide RRAM
Hon-Sum Philip Wong,Heng-Yuan Lee,Shimeng Yu,Yu-Sheng Chen,Yi Wu,Pang-Shiu Chen,Byoungil Lee,Frederick T. Chen,Ming-Jinn Tsai +8 more
TL;DR: The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide resistive switching random access memory (RRAM) are discussed, with a focus on the use of RRAM for nonvolatile memory application.
Journal ArticleDOI
Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies
Jiale Liang,H.-S. Philip Wong +1 more
TL;DR: In this article, the authors study the device requirements of a resistive cross-point memory array under the worst-case write and read operations and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size.
Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Journal ArticleDOI
Memory-bit selection and recording by rotating fields in vortex-core cross-point architecture
TL;DR: In this article, the authors proposed robust information storage, recording and readout, which can be implementaed in nonvolatile magnetic random access memories and is based on the energetically degenerated twofold ground states of vortex-core magnetizations.
Journal ArticleDOI
Memory-bit selective recording in vortex-core cross-point architecture
TL;DR: In this article, the authors proposed nonvolatile vortex random access memory (VRAM) based on the energetically stable twofold ground state of vortex-core magnetizations as information carrier.
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