Supporting information
for
Mobility engineering and metal-insulator transition in
monolayer MoS
2
Branimir Radisavljevic and Andras Kis
*
Electrical Engineering Institute, EcolePolytechniqueFederale de Lausanne (EPFL), CH-1015
Lausanne, Switzerland
*Correspondence should be addressed to: Andras Kis, andras.kis@epfl.ch
SUPPLEMENTARY INFORMATION
DOI: 10.1038/NMAT3687
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© 2013 Macmillan Publishers Limited. All rights reserved.
S1. Device fabrication
Degenerately-doped Si wafers covered with 270 nm thermally grown SiO
2
serve as the
substrate and back-gate for the MoS
2
devices. Single and few-layer MoS
2
flakes are obtained by
standard micromechanical cleavage technique.
1
Flakes are identified by an optical microscope
and their thickness is ascertained by optical contrast measurements
2
and atomic-force
microscopy. The source, drain and voltage probes were defined by electron-beam lithography
followed by deposition of 90 nm thick Au electrodes. In the inset of Figure 1a we present an
optical image of the device after standard lift-off procedure performed in acetone. In order to
remove resist residue and decrease contact resistance in our devices, we perform annealing at
200 ºC in Ar atmosphere for 2 hours. After this step, we shape the MoS
2
flakes into Hall bars
using oxygen plasma etching and an e-beam defined etching mask. Some of our devices were
further processed and a 30 nm-thick HfO
2
layer was deposited by atomic layer deposition (ALD)
followed by another e-beam lithography process defining the top-gate electrode. The top-gate
electrode is made by depositing Cr/Au (10/50 nm) layer by electron-beam evaporation and lift-
off in acetone. The optical image of one of our top-gated devices is shown in Figure 1a. All
devices are wirebonded onto chip carriers and transferred to a cryostat where the transport
measurements were performed in vacuum from room temperature down to 300 mK.
S2. Device details
We have performed measurements on two devices in single-gate configuration, two devices
in single-gate configuration covered with a 30 nm thick HfO
2
layer and six devices in dual-gate
configuration. Their characteristics are summarized in the following table:
Table 1.Device details
Device Configuration
W
(µm)
L
12
(µm)
k
F
·l
e
n
MIT
(10
13
cm
-
2
)
γ
μ
(cm
2
/Vs)
T=4K
μ
(cm
2
/V
s)
T=260K
Monolayer1 Single-gate 3.9 0.7 - - 1.4 6.4 17.2
Monolayer2 Dual-gate 3.0 1.2 1.8 1 0.3 87.7 56.9
Monolayer3 Dual-gate 3.7 - - - 1.29 50.1 16.5
Monolayer4 Dual-gate 3.0 1.4 0.9 - 0.52 46.2 13.9
Monolayer5 Dual-gate 1.9 1.6 2.5 1 0.73 174 63
Monolayer6 Dual-gate 2.3 2.00 1.76 - 0.53 60 31.1
Monolayer7 Single-gate,
with dielectric
3.20 1.3 - - - 30.9 30.6
Double-layer Dual-gate 1.6 1.6 2 1.3 1.47 117.6 26.4
Three-layer Single-gate,
with dielectric
4.9 1.8 2 1.1 0.75 84 24
Four-layer Single-gate 4.6 1.3 - - - 1 30.1
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DOI: 10.1038/NMAT3687
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W is the channel width and L
12
is the distance between voltage probes used in four-contact
measurements. k
F
·l
e
is the Ioffe-Regel parameter related to the metal-insulator transition point
and n
MIT
is the electron concentration at which the transition occurs, extracted from Hall-effect
measurements.
S3. Top-gate efficiency
We have performed measurements on six devices in double-gate configuration where the
electron concentration in the MoS
2
channel can be as high as 3.6 · 10
13
cm
-2
due to a very
efficient top-gate, Figure S1.
Figure S1. Electron concentration n
2D
extracted from R
xy
for different values of the top-gate voltage V
tg
demonstrating electron concentration as high as 3.6 · 10
13
cm
-2
. Measurements were performed on the
device Monolayer2 from Table 1.
S4. Schottky barrier height in a single-gate device
From the temperature dependence of conductance for different gate voltages (Figure 2b in
the main text) we were able to extract activation energy E
a
dependence on gate voltage V
bg
,
Figure S2. From the deviation of the E
a
from the linear trend, occurring when barrier tunneling
becomes the dominant mechanism for charge carrier injection, we estimate a Schottky barrier
height Φ
SB
∼ 45meV. This value is relatively small and does not have a significant influence on
our mobility extraction from four-contact measurements.
3.6
3.4
3.2
3.0
2.8
2.6
Electron concentration n
2D
(10
13
cm
-2
)
3210-1
Top-gate voltage V
tg
(V)
C
tg-Hall
/e = 2.7 · 10
12
F/(C cm
2
)
n = n
o
+C
tg-Hall
·V
tg
/e
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DOI: 10.1038/NMAT3687
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Figure S2. Activation energies E
a
for monolayer MoS
2
in a single-gate configuration in the
insulating regime. Dependence of activation energy E
a
on V
bg
. From the deviation of the E
a
from the
linear trend, occurring when barrier tunneling becomes the dominant mechanism for charge carrier
injection, we estimate a Schottky barrier height for the charge carrier injection from gold electrodes into
monolayer MoS
2
of Φ
SB
∼ 45 meV.
S5. Hysteresis in G - V
tg
curves
Double sweeps of conductance G as a function of the top gate voltage V
tg
at several
temperatures for the double-gated device presented in the manuscript are shown in Figure S3
demonstrating no hysteresis for all temperatures. This excludes the possibility of device
hysteresis being behind the observation of the metal-insulator transition.
Figure S3. Conductance G double-sweeps as a function of the top gate voltage V
tg
at several
temperatures for the double-gated device presented in the manuscript demonstrating no hysteresis for
all temperatures, excluding the possibility of its influence on the MIT.
80
60
40
20
Activation energy E
a
(meV)
40302010
Back-gate voltage V
b
g
(V)
300
250
200
150
100
50
0
Conductance G (µS)
-4 -2 0 2 4
Top-gate voltage V
t
g
(V)
T = 4.2 K
40 K
80 K
120 K
180 K
240 K
V
ds
= 500 mV
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DOI: 10.1038/NMAT3687
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S6. Capacitance determination
We extract device capacitance from Hall effect measurements and the transverse Hall
resistance R
xy
for all MoS
2
devices covered with a dielectric layer in order to accurately
determine the mobility. The contact resistance for uncovered devices is too large to perform
meaningful R
xy
measurements. From the inverse slope of R
xy
vs magnetic field (an example is
shown on figure 5a in the main manuscript), we can directly determine the electron density n
2D
in
the MoS
2
channel. The variation of the electron density extracted from R
xy
as a function of the
control-gate voltage for two typical situations encountered in the literature is shown in Figure S4.
In Figure S4a, we show the dependence of the charge density on the back-gate voltage for a
device in which the MoS
2
channel is covered with a 20nm thick HfO
2
layer. From the slope, we
can extract the correct capacitance of the back-gate, C
bg-Hall
, which in this case is 2.4 times higher
than the capacitance calculated using the parallel-plate capacitance model
geom 0 ox,bottom
/
r
Cd=ε ε
.
The capacitive coupling between the MoS
2
channel and the back-gate is therefore increased due
to the presence of the dielectric covering MoS
2
and any mobility estimate that would use the
geometric capacitance instead of would yield a mobility value overestimated by a factor of 2.4.
Similarly, in Figure S4b we present charge density measurements for a device in which the top
gate has been disconnected. In this case we find that the capacitive coupling is increased by a
factor of 53. This shows that using the parallel-plate capacitance model in place of an actual,
measured capacitance in this type of situations can result in underestimating the strength of the
capacitive coupling and field-induced charge density and lead to an overestimated mobility.
Figure S4. Electron concentration n extracted from R
xy
for different values of the control gate
voltage. a, Charge density vs. bottom gate voltage for the three-layer device from Table 1. The
conductivity is controlled using a bottom gate, while the channel is covered by a 30 nm thick HfO
2
layer.
The presence of the dielectric increases the back-gate capacitance by a factor of 2.4 with respect to the
parallel-plate capacitance, commonly used for mobility estimates. b, Charge density vs. bottom gate
voltage for the top-gated monolayer device (monolayer 4 in Table 1) measured as a function of the
bottom gate while the top gate is disconnected. The capacitance is increased by a factor of 53 with
respect to the parallel-plate capacitance where one plate is the back-gate and the other the MoS
2
channel.
ab
3.0
2.5
2.0
1.5
1.0
Electron concentration n (10
13
cm
-2
)
1098765
Back gate voltage V
bg
(V)
C
bg-Hall
= 6.88 · 10
-7
F/cm
2
C
bg-geometric
= 0.13 · 10
-7
F/cm
2
C
bg-Hall
/C
bg-geometric
= 53
1.1
1.0
0.9
0.8
0.7
Electron concentration n (10
13
cm
-2
)
8075706560
Back gate voltage V
bg
(V)
C
bg-Hall
= 3.4 · 10
-8
F/cm
-2
C
bg-geometric
= 1..26 · 10
-8
F/C·cm
-2
C
bg-Hall
/C
bg-geometric
= 2.4
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DOI: 10.1038/NMAT3687
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