Modeling of Pocket Implanted
MOSFETs
for Anomalous Analog Behavior
Kanyu Mark Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth*, Keith Green*, John Krick*,
Tom Vrotsos*, and Chenming Hu
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Tel:
5
10-643-2639 Fax:
5
10-643-2636 Email:
kcao@cory.eecs.berkeley.edu
*Spice Modeling Laboratory, Texas Instruments, Dallas, TX 75266, USA
Abstract
Pocket implant is widely used in deep-sub-micron CMOS
technologies to combat short channel effects. It, however,
brings anomalously large drain-induced threshold voltage shift
and low output resistance to long channel devices. This cre-
ates a serious problem for high-performance analog circuits.
In this paper, the first physical model of these effects are pro-
posed and verified against data from
a
0.18pm technology.
This model is suitable for SPICE modeling.
Introduction
Pocket implant is widely used in deep sub-micron CMOS
technologies to reduce
VT
roll-off and punch-through
[
11. This
technique, however, produces large drain-induced
VT
shift and
low
R,,,
in long channel devices [2], greatly affecting analog
circuit design and performance. Physical compact model for
these effects, however, is not available.
In this work, we report the first physical model of these ef-
fects suitable for compact MOSFET modeling. The proposed
model is verified against both simulation and experimental
data from a 0.18pm CMOS technology.
Drain-induced threshold voltage shift (DITS)
Fig. 1 illustrates the enhanced DITS effect in long channel
devices with pocket implants compared with uniformly doped
devices using 2-D simulation. Fig. 2 is an illustration of the
structure used in the device simulation. DITS increases by 2 to
3
times for long channel devices. Fig. 3 shows the simulated
q~\
vs.
x
for two
V,,
biases for a pocket implanted device.
Clearly,
q\
is independent of
x
in the center segment of the
channel and the drain barrier peak decreases with increasing
V,, thus leading to DITS. Starting with the drift-diffusion
equation, we derived
a
drain current expression by consider-
ing the source-end, center, and drain-end sections of the chan-
nel separately and applying a DIBL model [3] to the drain-
side barrier only:
5,
Tu
1
-
=
AW
I,
I
yWwD6
-
e+*
)
c
I-
-
e-P(c"s*-c"m,"l)@qN
p
x
dep-&"x(vTo
-vFB-~~)/I;,I/&,lx~~~I
(2)
~o~e-~~~,-~~,wr~~~y
P&~~(v~
- -
2~n)
C,L
+
(1
+
e-clv*
)
(1)
where
p=&g,
p,
is the surface potential, and
CI
and
C2
as
C,
=p
(,LP'ZP +&-LP'lP)
are model parameters.
1,
=
Jm'.
If
V,
is defined to be
the gate voltage at which
Id,=Icnr=IT.WIL,
where
IT
is the
threshold current chosen experimentally. Then the threshold
voltage shift can be derived as:
where
S
is the sub-threshold swing and can be calculated
or
extracted [4].
Modeling the output resistance
Pocket implants also lower the output resistance,
R,,,.
Figure
4 shows that at low
V,,,
R,,,
can be 10 to
100
times smaller
because of the pocket implant. Pocket implants affect output
resistance in two ways. Firstly, DITS causes
Zh
to increase
with increasing
V,.
The early voltage due to this mechanism
can be derived from (1):
Since parameters
CI
and
C2
in
(1)
are used to model
Zd,
in
subthreshold-threshold region, we introduce parameters
CoC,
C,,,
and
C2,
to accurately capture this effect in strong inver-
sion region:
The second effect of the pocket implant on
R,,,
is that the out-
put resistance due to all mechanisms (CLM, DIBL, etc.) is
reduced by
a
factor that varies with
V,,
and
L.
Let us compare
a pocket-implanted device with a MOSFET uniformly doped
to the pocket concentration,
N,,.
In Figure
5,
both devices are
partitioned into two parts. The device on top has a length
L,,,
the length of the pocket. The lower part is the rest of the chan-
nel with length
L-L,,.
This partition is useful because in the
saturation region, is mainly determined by the effects in a
small region close to the drain, and the rest of the channel, i.e.
the lower device may be considered simply
a
source resis-
tance. For the cascode circuit in Fig. 5(a), the output resis-
tance in saturation
is
well known:
where
rol
is the output resistance of the device on top. In
a
similar way,
%,,
of the pocket device, i.e. the circuit in Fig.
5(b) can be derived as:
R,,,
=
(g,,,,r,,
+
1).
rC,,
=
(LI
Lp).
r,,l
(5)
where
hv,
=v,(N,)-v,(N,,,~).
Since MI and Mi, have the same
doping and since Early voltage
VA
is insensitive to
Vg,r,
Mi and
MI, should have the same
VA.
0-7803-5410-9/99/$10.00
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1999
IEEE
['.a.
I
c.1
IEDM
99-171
Considering
sv,
<<
(v,
-
vT)
,
using equations
(5),
(6) and (7)
the output resistance of the pocket-implanted device can be
rewritten as:
(8)
where
R,,,
is the output resistance of the uniformly doped
device, which can be modeled by conventional models such as
BSIM3v3 [4].
F
is
a
“degradation factor”
Routp
=
F.
ROU,
where
PF
SV,
I
L
should be considered a fitting pa-
rameter decided by the characteristics of pocket implant.
G
Results and‘Discussion
Eq. (3) can be added to
a
conventional
VT
model as a new
term. Fig.6 shows the agreement between the model and the
measured
VT
of a WbSpm/lOpm device. Fig.
7
shows that
the BSIM3
VT
model [3] does not model the
Vll,T
dependence
of
VT
at long gate lengths. Fig.
8
shows that the new model
significantly improves the fitting using parameters extracted
from Fig.
6.
The new threshold shift model can give rise to
DITS at long channel lengths where the conventional DIBL
theory predicts none. This can be explained by the fact that at
Vg-VT
and small
Id,,,
there is little voltage drop in most of the
channel region. Therefore, even in
a
long channel device,
nearly all the
Vd,T
is available to reduce the drain-side barrier
height as shown in Fig.
3
and the drain barrier height can sig-
nificantly affect
IdT.
To verify the model of (9), 2-D simulations and meas-
urements are performed for identical devices with and without
pocket implant. Fig.
9
shows that the “degradation factor” is
indeed a constant, independent of
Vds
in the saturation region
which
is
in agreement with
(9).
Our derivation
is
general and
does not depend on what mechanisms determine the
kUt.
From the model, at high
V,,,
and long
L,
if
F
is plotted versus
cv,,
-vr)lfi,
all data should fall on
a
universal curve. This is
verified in Fig.
10.
F
vs.
V,,
for different
L
also agrees with
the 2-D device simulation data in Fig. 11. In Fig. 12, this
model of the degradation factor is compared with the ratio of
output resistance measured on devices with and without
pocket implants. The devices are otherwise identically fabri-
cated using a 0.18
pm
process. The agreement is excellent.
The proposed model not only provides the first physical
analysis for the anomalous analog behaviors but is also suit-
able for use in compact modeling of analog devices. It was
implemented into the BSIM3 model and model parameters
were extracted for a 0.18pm technology. Fig. 13 shows that
the output resistance fitting is excellent and the fitting in long
channel, low
V,,T-V~
region has been significantly improved.
Both the threshold voltage model and the output resistance
model are reduced to the original model when
IK,,
C,,,
and
SVT
approach zero. In that case,
AVFO
in (3),
VA,Dms=co
in
(4a), and
F=l
in (9) respectively.,Also from the expression,
we can see that to minimize the degradation of the output re-
sistance, pocket implant with lower peak concentration and
wider lateral length is desired. These are also the conditions to
minimize the long channel DITS effect. This agrees with the
fact that output resistance degradation and long channel DITS
are highly correlated [2]. Although the models are developed
for pocket implanted devices, it can also improve the model
accuracy of devices without pocket implant if it has reverse
short channel effect (RSCE) due to defect-enhanced diffusion.
Acknowledgements
The authors want to thank
Joe
Watts and Peiqi Xuan for dis-
cussions and BTA for providing model development tool. The
work is supported by SRC under contract 98-SJ-417, Compact
Modeling Council, and Texas Instruments under the MICRO
program.
References
[I]
M.Rodder et
al.,
“A 0.10pn Gate Length CMOS Technology with 30A
Gate Dielectric
for I.0V-1.5V Applications,” IEDM Tech. Digest, p
223,
1997.
[2]
A. Chatterjee
et
al.,
“Transistor Design Issues in Integrating Analog
Functions with High Performance Digital CMOS,” Proc. VU1 Sypm.,
pp.147, 1999.
[3] Zhi-Hong
Jiu
et al.,
“Threshold Voltage Model for Deep-Submicrometer
MOSFET’s,”
IEEE
TED
Vol.
40,
No.
1,
pp. 86, Jan. 1993.
[4]
Weidong Liu
et
al.,
BSIM3v3.2 MOSFET Model User’s Manual (1998).
pp. 3-10.
http://www-device.eecs.berkeley.edu/-bsim3/.
-w-
Device with pocket
-a-
Device without pocket
9
E
J..,.,.,.,.,.
0
2
4
6
8
10
Gate Length
(urn)
Fig.
1.
Comparison
of
(Vnin-V~st) vs.
L
between two devices with and
without pocket implant by 2-D simulation.
The
threshold voltage shift is
2-3 times larger
for the pocket implanted device at long gate lengths.
T0,=4nm
I
I
NSub=4E 17 cm-3
Fig. 2. Device structure used in 2-D device simulations. Pocket doping
profile shown simulates that
of
a 0.18pm technology.
7.5.2
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v)
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(d
C
a,
0
a,
-e
3
(I)
a
-
.-
c
c
a
8
0.324-
h
2
a,
0.322-
c
-
P
0.320-
I:
v)
s
E
0.318-
k
Fig.
3.
Simulated channel surface potential. Only the drain barrier is
significantly affected by
Vd,.
The integration in
F.q.
I
is carried out in
regions TI, Tz, and T1.
.___.
I”
*
a)
Uniform
(b)
Pocket
Fig.
5.
Equivalent circuits usedin the derivation of the output resistance
model.
A
uniformly doped device is shown in
(a)
and
a
pocket implanted
device in
(b).
o.6
1
0
V,,i, (V,,=O.OSV)
0
V,,,, (Vd,=l.50V)
I-
Previous
Model
h
Average Doping+V,
roil-off
c
0
II.
v)
a,
2
0.3-
0.1
1 10
Gate Length
(urn)
\
Fig.
7.
Best-effort fitting of experimental data with the
BSIM3
model.
The model shows negligible
DIBL
effect
(V,
dependence) at long gate
lengths.
h
E
I:
9
a,
0
C
(d
v)
v)
W
[r
3
Q
c
.-
c
c
a
-I-
I?,”,,
N~ub=4E17crn~3,N,=8E1 7~rn’~
+-
Roul,
Nsub=4E17crn”
1 10
Gate Length (urn)
Fig.
4.
Simulated
R,,
of the device with pocket implant is
more
than 10
times smaller at long channel length. One device has a pocket doping
of
NP=8E17cm”, and pocket length
I,,=O.OIpm.
The devices
are
otherwise
identical.
I
,
.
,
.
,
.
,
,
0.0
0.5 1
.o
1.5
VdS
(VI
Fig.
6.
The proposed model is in excellent agreement with measured
VT
vs.
V,
of
a
10pm MOSFET fabricated using
a
0.18pm
process with
pocket implantation.
Vds=l.5OV Data
Old model in
Fig.
7
+new model
0.6
-
m
0
’
0.4-
0
c.
v)
$
0.3-
4)
9
I-
’1
0.1
1
10
Gate Length (urn)
Fig.
8.
Fitting of experimental
data
with the new model added to the
BSIM
model
used
in Fig.
7.
The number of fitting parameters is the same
as
in Fig.
7
because parameters extracted in Fig.
6
are used in the new
model.
7.5.3
IEDM
99-173
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100
q
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1.5~10~-
c
80
p
60
2
1.0x108-
-"
1
cc
I
+Degradation Factor
I
-El-Output Resistance
0.0
of
uniform device
4
................................
IO
0.0
0.5
1
.o
1.5
v,,
(VI
Fig.
9.
Degradation Factor of output resistance from 2-D simulation is
almost independent of
V,
as
predicted by the proposed model in both
channel length modulation (CLM) and drain-induced barrier lowering
(DIBL) regions.
g
0.1
b
0.3
0.2
0.0
0.4
0.6
0.8
1
.O
1
.2
1
.4
1
.6
1
.8
2.0
2.2
vg,
(V)
Fig. 11. Agreement of
V,,
dependence of the degradation factor F be-
tween model and simulation for different gate lengths.
D
WSLO1S-l.IV WILs.oo/o.15
Td7C
VB=Oo.OO V
loo0j
.:,-gy/
Model
(V
gs-v,,)~sq
NL)
Fig. 10. Simulation verification of the predicted universal curve of the
degradation factor (1IFplotted) vs.
(v,,~
-vT,,)/fi.
1
10
Gate Lenath
(urn)
Fig.
12.
Agreement of model and experimental data of
a
0.18pm process
with and without pocket implant. Note that the degradation factor is very
different from Fig.
9,10,11
because the uniform device is doped to the
substrate level.
6.1
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3.66
s
2
2.44
U
1.22
0.0
W51025-l.lV WA-5.WIO.25
Td7C
VB=O.OO V
29
0
___.
VGS(V)=
ow
120
15.2
23
2
005
037 069 101 133 165
Rmr
En%=
4
25
VD
(V)
MaxEnY.=
1098
W5L08-1.IV w11=5.w1o.80
Td7C
VBso.00
v
9 12Sl
005
037
069
101
133
165
Rms
Em%=
3
48
(V)
Max
En'/=
e
49
9.8003
7.0403
z
5.8803
B
s
5
3.9203
1.9603
O.M&
C
Fig.
13.
On the left, the equivalent circuit of the implementation of proposed model. On the right is the fitting of measured
Rou,
of 0.18pm technology
using the model implemented.
12 devices with gate lengths from 0.15pm to 10pm are fitted using
a
single set of parameters without binning. The
maximum error is
17.0%
and the RMS
error
is
4.9%.
A new
V,,,
model and CLM
R,,
model were
also
implemented for the fitting.
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