Showing papers on "Diffusion capacitance published in 2006"

Methods and systems for detecting a capacitance using switched charge transfer techniques

Abstract: Methods, systems and devices are described for detecting a measurable capacitance using charge transfer techniques. According to various embodiments, a charge transfer process is performed for two or more times. During the charge transfer process, a pre-determined voltage is applied to the measurable capacitance, and the measurable capacitance is then allowed to share charge with a filter capacitance through a passive impedance that remains coupled to both the measurable capacitance and to the filter capacitance throughout the charge transfer process. The value of the measurable capacitance can then be determined as a function of a representation of a charge on the filter capacitance and the number of times that the charge transfer process was performed. Such a detection scheme may be readily implemented using conventional components, and can be particularly useful in sensing the position of a finger, stylus or other object with respect to an input sensor.

High dynamic range pixel amplifier

Abstract: A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate having source and drain regions commonly connected to the floating diffusion region. The gate has an intrinsic capacitance which, when the gate is activated, is added to the capacitance of the floating diffusion region, providing a low conversion gain readout. When the gate is off, the floating diffusion region capacitance is minimized, providing a high conversion gain readout. The gate may also be selectively switched to mid-level. At mid-level, a mid-level conversion gain, which is between the high and low conversion gains, readout is provided, but the gate still provides some capacitance to prevent the floating diffusion region from saturating.

Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures

Abstract: A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

Application of junction capacitance measurements to the characterization of solar cells

Abstract: The quasi-static capacitance-voltage ( C-V) technique measures the dependence of junction capacitance on the bias voltage by applying a slow, reverse-bias voltage ramp to the solar cell in the dark, using simple circuitry. The resulting C-V curves contain information on the junction area and base dopant concentration, as well as their built-in potential. However, in the case of solar cells made on low to medium resistivity substrates and having thick emitters, the emitter dopant profile has to be taken into account. A simple method can then be used to model the complete C-V curves, which, if the base doping is known, permits one to estimate the emitter doping profile. To illustrate the method experimentally, several silicon solar cells with different base resistivities have been measured. They comprise a wide range of areas, surface faceting conditions and emitter doping profiles. The analysis of the quasi-static capacitance characteristics of the flat surface cells resulted in good agreement with independent data for the wafer resistivity and the emitter doping profile. The capacitance in the case of textured surfaces is a function of the effective junction area, which is otherwise difficult to measure, and is essential to understand the emitter and space charge region recombination currents. The results indicate that the effective area of the junction is not as large as the area of the textured surface.

Charge-based capacitance measurement for bias-dependent capacitance

Abstract: In this letter, charge-based capacitance measurement (CBCM) is applied to characterize bias-dependent capacitances in a CMOS transistor. Due to its special advantage of being free from the errors induced by charge injection, the operation of charge-injection-induced-error-free CBCM allows for the extraction of full-range gate capacitance from the accumulation region to the inversion region and the overlap capacitance of MOSFET devices with submicrometer dimensions.

Technique for reducing capacitance of a switched capacitor array

Abstract: A circuit reducing the capacitance of a switched capacitor array by mitigating switch capacitance. Reducing the effect of switch capacitance increases the frequency range of an inductor-capacitor tank containing the switched capacitor array. A pull-up circuit is coupled between a voltage source and a node. A switched capacitor and a switch are coupled to the node. The pull-up circuit biases the switch to reduce switch junction capacitance when the switch is off. In an example, a pull-up resistor is coupled between the node and a voltage source to bias the switch. In another example, a pull-up switch and pull-up resistor are coupled between the node and a voltage source to bias the switch.

The Physical Background of JUNCAP2

Abstract: A new physics-based junction model for CMOS, called JUNCAP2, is presented. It contains new single-piece formulations for the Shockley-Read-Hall generation/recombination current and the trap-assisted tunneling (TAT) current, which are valid both in forward and reverse mode of operation. Moreover, the TAT model extends the existing model (IEEE Trans. Electron Devices, vol. 39, p. 2090, 1992) to the high electric fields encountered in today's CMOS technologies. Furthermore, the model contains expressions for junction capacitance, ideal current, band-to-band tunneling current, avalanche breakdown, and junction shot noise. The parameter extraction is also discussed in this paper

Semiconductor device and manufacturing method therefor

Abstract: PROBLEM TO BE SOLVED: To provide a horizontal-type bipolar junction transistor, having a performance similar to the performance of a high-speed vertical type bipolar junction transistor. SOLUTION: There is included a PSWS (polysilicon sidewall spacer) which forms a contact region 112, contacting with a base region 110 of a vertical type bipolar junction transistor 100. Accordingly, a processing step of aligning a contact mask in the relatively narrow base region 110 is eliminated. Self matching of a base/emitter region is made by this sidewall spacer, and the base resistance and the junction capacitance are reduced. Accordingly, the cut-off frequency f τ is improved, and the oscillation frequency f max can be made maximum. Furthermore, a BiCMOS (bipolar CMOS) technique can be executed on an insulating substrate, such as SOI, using this new topology. COPYRIGHT: (C)2006,JPO&NCIPI

Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate

Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

A novel method of electrical characterization of a semiconductor diode at forward bias

Abstract: A novel nondestructive method to characterize a semiconductor diode using admittance–voltage (A–V) measurements at forward bias is presented. For this method, the imaginary and the real part are considered simultaneously to get the accurate parameters of a diode, such as series resistance, junction capacitance, junction voltage and ideality factor at various forward biases. This method can also be used to detect and measure an interfacial layer in a real diode. With this method the n-GaN Schottky diodes with various ohmic contacts were investigated. The measurements confirmed that the giant negative capacitance (NC) of Schottky diodes is an effect of the junction and the interfacial layer can be considered as a layer structure with nonlinear resistance and capacitance.

Deep ultraviolet detection dynamics of AlGaN based devices

Abstract: The photoconductive response of AlGaN based UV detectors to 193nm excimer laser radiation is presented. Two devices have been tested: a metal-semiconductor-metal (MSM) planar structure and a Schottky diode. The transient response of the MSM device closely follows the laser pulses, with a photoconductive decay time constant shorter than 3ns. Conversely, the Schottky diode shows a slower photoconductive rise and decay kinetics due to the material series resistance coupled with the junction capacitance. Moreover, a longer time constant tail is also evident in this case with a characteristic time of about 40ns, due to the presence of trap states localized at 0.2–0.3eV from the band edge. The detection dynamics has been evaluated by changing the beam energy density between 2×10−5 and 0.2mJ∕mm2. The signal increases linearly in the case of the MSM device up to 0.001mJ∕mm2, whereas, for a further intensity rise, the response shows a sublinear behavior. On the contrary, the Schottky diode showed a linear trend in...

220-MHz monolithically integrated optical sensor with large-area integrated PIN photodiode

Abstract: We propose a PIN photodiode integrated in a BiCMOS process which combines a quantum efficiency of nearly 100% for red light, fast response times, and a low junction capacitance. Bandwidths of 720 MHz at 660 nm and 683 MHz at 850 nm are achieved for this PIN photodiode. It allows the design of fast optoelectronic integrated circuits for many advanced applications in optical sensing, optical storage systems, and optical data transmission for optical wavelengths ranging at least from 660 to 850 nm. Because of the low photodiode capacitance of 0.01 fF//spl mu/m/sup 2/, it is possible to achieve high bandwidths, even with large photodetector areas. The proposed optical receiver employing a PIN photodiode with a diameter of 500 /spl mu/m and a capacitance of only 2.2 pF attains a -3-dB bandwidth of 220 MHz, which corresponds to a maximum nonreturn-to-zero data rate of 300 Mbit/s.

Charge accumulation capacitance sensor with linear transfer characteristic

Abstract: A method and apparatus for capacitance sensing uses an offset feedback voltage to linearize a charge-transfer characteristic.

New method for threshold voltage extraction of high-voltage MOSFETs based on gate-to-drain capacitance measurement

Abstract: This letter reports on the extraction of the threshold voltage of laterally diffused MOS transistors. A clear analysis of the device physics is performed, highlighting the correlation between the change of the electron charge distribution along the channel and the device capacitance variations when the gate voltage is swept. Using numerical simulations, it is shown that the peak of the gate-to-drain capacitance is related to the transition of the surface from weak to moderate inversion in the intrinsic MOS transistor at the location of the maximum doping concentration, which corresponds to the threshold voltage of the device according to the MOS theory. Comparison between conventional I/sub D///spl radic/g/sub m/ extraction and the new proposed capacitance peak method is performed on both technology computer-aided design simulations and measurements in order to confirm the new experimental technique and related theory.

Method and Apparatus for Modeling Diffusion in an Electrochemical System

Abstract: A method for determining a diffusion voltage in an electrochemical cell (e.g., a battery used in connection with an automotive vehicle) includes estimating a previous diffusion voltage, calculating a new diffusion voltage using an equation based on a diffusion circuit model and the previous diffusion voltage, and setting the previous diffusion voltage equal to the new diffusion voltage. The step of calculating the new diffusion voltage may then be repeated.

Characterization of ultrasmall all-Nb tunnel junctions with ion gun oxidized barriers

Abstract: We have fabricated ultrasmall all-Nb tunnel junctions and single electron transistors using shadow evaporation combined with in situ ion gun oxidation. Basic parameters of the Nb/Nb-oxide/Nb junctions, namely, the barrier height, width, and specific junction capacitance, are estimated from the transport characteristics.

A compact model for SiGe HBT on thin-film SOI

Abstract: Heterojunction bipolar transistor (HBT) fabrication on thin-film silicon-on-insulator (SOI) has been recently demonstrated. Due to the space volume constraint (thin film) for the device fabrication, the HBT structure is different from bulk HBT. In fact, compared to a bulk device, the buried layer has been suppressed and a lateral collector contact configuration is introduced. This device features a vertical expansion followed by a lateral expansion of the base-collector space charge region. This nonconventional charge behavior induces a kink in the base-collector junction capacitance characteristics, and as a consequence a modified Early effect. Furthermore, the low current transit time is modified compared to a bulk HBT. In this paper, all these effects are analyzed and a compact model for SOI-HBT is proposed. The model is validated on real SOI-HBTs with different collector doping levels.

Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics

Abstract: Optoelectronic and electrooptic elements are integrated on VLSI chips. The junction capacitance of a nano-photodiode is extremely low ( 150pm/V) suitable for on-chip modulators. This paper introduces a new approach for realizing high-speed optical interconnects on silicon chips. This concept uses nano-photodiodes on silicon with extremely low parasitic capacitance (less than 10aF) enabling robust communication at very high frequencies. The results demonstrate 5GHz clocking with the promise of up to 20GHz. The authors will also discuss how the silicon nano-photodiode can be used for wavelength-division multiplexing and low-voltage electro-optic modulators for on-chip and off-chip optical communications

User-definable, low cost, low phase hit and spectrally pure tunable oscillator

Abstract: A tunable oscillator includes a first transistor, a second transistor connected in parallel with the first transistor, a noise feedback and bias network coupled to the first and second transistors, a planar coupled resonator network coupled to the transistors and a means for dynamically tuning the resonant frequency of the planar coupled network and the junction capacitance of the transistors.

Physics-based modeling and characterization for silicon carbide power diodes

Abstract: Silicon carbide Schottky, merged PiN Schottky (MPS), and PiN diode technologies are modeled for on-state and reverse recovery conditions. The on-state operation of the PiN diode is modeled through four unique regimes of operation, including current densities resulting in emitter recombination, which results in a stored charge plateau during reverse recovery of SiC PiN diodes. An expression for the moving boundary redistribution capacitance is developed to accurately describe the reverse recovery process in PiN diodes. Furthermore, the extraction of stored charge and junction capacitance from transient reverse recovery measurements is also demonstrated for all diode technologies. The on-state operation of Schottky and merged PiN Schottky diodes is described and a method to model the surge current in MPS diodes is discussed. The performance of the model is demonstrated for a commercially available 600 V, 4 A Schottky diode and a 10 kV, 7.5 A PiN diode. Measurements demonstrating the extraction of model parameters and model validation results are included.

Void formation for semiconductor junction capacitance reduction

Abstract: Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and thermal annealing method. The ion implantation and thermal annealing method provides for a plurality of voids located completely within the active semiconductor layer proximate to the semiconductor junction located within the active semiconductor layer, absent stressing of the active semiconductor layer.

Linear theory of the quasi-unipolar photodiode

Abstract: Quasi-unipolar (QU) operation, in which unequal numbers of electrons and holes participate in the photocurrent, is proposed as a strategy for optimizing III-V photodetector bandwidth. Analytic expressions are derived for the transport of photogenerated charge, based on a linearization of the first two moments of the Boltzmann transport equation. Microscopic charge and current densities are shown to imply an equivalent circuit model for the QU detector, for which the familiar heterojunction p-i-n and unitraveling-carrier detectors are limiting cases. Simulations demonstrate that a maximum 3-dB bandwidth may be achieved via a QU rather than a purely bipolar or unipolar operation and without penalty to junction capacitance or quantum efficiency.

Time-resolved measurement of capacitance in a Josephson tunnel junction

Abstract: The capacitance of a Josephson tunnel junction is an important parameter, which determines its plasma frequency ωp and thus the energy level spacing in the quantum regime. When a microwave signal at the frequency of ω is applied to a current-biased junction in its zero-voltage state, the escape rate from this state is somehow enhanced. The enhancement is expected to go through a pronounced maximum when ωp=ω. Making use of such microwave generated resonant activation in the thermal regime, we have developed a time-resolved measurement scheme for determining the junction capacitance with an uncertainty of less than 2%.

Study on Intrinsic Loss of Unipola Power Device due to Main Junction Capacitance

Abstract: The converters with high power output density has been envisioned for next generation. The key to realize that is operation at very high switching speed and utilization of ultra low loss of power semiconductor devices in wide bandgap semiconductor e.g. Silicon Carbide and superjuction. The power loss by main junction capacitance, Coss intrinsically structured inside the device has been reported but the quantitative study is not adequate. In this study, for 3kW converters, the loss by Coss is theoretically and experimentally proved using heat measurement with resistive and inductive load chopper circuit with 500V Si-MOSFET and 600V Silicon Carbide Schottky barrier diode. Moreover since large loss remained other than already known loss factors has been quantitatively revealed, and it is suggested that this remained loss will be a next target for further reduction of switching loss.

An improved junction capacitance model for junction field-effect transistors

Abstract: A new junction capacitance model for the four-terminal junction field-effect transistor (JFET) is presented. With a single expression, the model, which is valid for different temperatures and a wide range of bias conditions, describes correctly the JFET junction capacitance behavior and capacitance drop-off phenomenon. The model has been verified using experimental data measured at Texas Instruments.

Study on a Diode-bridge Type Capacitance Detection Circuit for Differential Capacitive Sensor

Abstract: Diode-bridge type capacitance detection circuit was developed in order to detect very small variation of differential capacitances in higher resolution. The circuit was designed for a comb structure tilt sensor, which was made of quartz crystal and had several movable electrodes between fixed electrodes. The circuit's output was almost proportional to the displacement of the movable electrode. Over 100 kHz AC voltage was supplied to obtain output signal sufficiently. In order to prevent decrease of the sensitivity, the diode-bridge part was composed of commercial PIN diodes, which had very low junction capacitance (less than 1 pF), and was mounted in small ceramic package with the tilt sensor. At present, the resolution of 0.0015 degree was obtained using the combination of the sensor and the detection circuit. It corresponded to the resolution of about less than 4.5 aF.

Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.

RF DMOS power device

Abstract: RF DMOS power device belongs to semiconductor power device technology and RF integrated circuit technique field. It contains adding doped n or P) buried layer below site partial oxidation partial oxidation insulating layer in current part SOI RF DMOS power device, making part SOI RF DMOS device having buried layer, utilizing PN node principle to increase lower pole plate junction capacitance corresponded exhaustion width of drain region/epitaxial layer junction, wherewith to reduce output capacitance, thereby raising device output power, using part air space insulation layer substituting partial oxidation insulating layer also capable of making part SON RF DMOS device, utilizing interstice relative dielectric constant being 1 property to reduce device output capacitance and raise device output power, utilizing part air space insulation layer and low doped n (or P) buried layer to make part SON RF DMOS device having buried layer capable of preferable reducing device output capacitance and raising output power. Said invented device works on microwave band frequency, at the same time having higher pressure resistance, heat dispersion and frequency response performance.