Showing papers on "Field-effect transistor published in 1991"

Improved Analysis of Low Frequency Noise in Field‐Effect MOS Transistors

Abstract: An improved analysis of low frequency trapping noise in a MOS device is proposed. This analysis takes into account the supplementary fluctuations of the mobility induced by those of the interface charge. It enables an adequate description of the gate voltage dependence of the input equivalent gate voltage noise to be obtained in various actual situations. The outputs given by the Hooge mobility fluctuation model are also presented and discussed with respect to those obtained by the carrier number fluctuation model. In particular, the impact of the channel length or channel width, and the model type on the input gate voltage and drain current noise characteristics is studied and compared to typical experimental data. Finally, a procedure for the diagnosis of the low frequency noise sources in a MOS transistor is proposed.

A neuron-silicon junction: a Retzius cell of the leech on an insulated-gate field-effect transistor.

Abstract: An identified neuron of the leech, a Retzius cell, has been attached to the open gate of a p-channel field-effect transistor. Action potentials, spontaneous or stimulated, modulate directly the source-drain current in silicon. The electronic signals match the shape of the action potential. The average voltage on the gate was up to 25 percent of the intracellular voltage change. Occasionally weak signals that resemble the first derivative of the action potential were observed. The junctions can be described by a model that includes capacitive coupling of the plasma membrane and the gate oxide and that accounts for variable resistance of the seal.

The potential of diamond and SiC electronic devices for microwave and millimeter-wave power applications

Abstract: The potential of SiC and diamond for producing microwave and millimeter-wave electronic devices is reviewed. It is shown that both of these materials possess characteristics that may permit RF electronic devices with performance similar to or greater than what is available from devices fabricated from the commonly used semiconductors, Si, GaAs, and InP. Theoretical calculations of the RF performance potential of several candidate high-frequency device structures are presented: the metal semiconductor field-effect transistor (MESFET), the impact avalanche transit-time (IMPATT) diode, and the bipolar junction transistor (BJT). Diamond MESFETs are capable of producing over 200 W of X-band power as compared to about 8 W for GaAs MESFETs. Devices fabricated from SiC should perform between these limits. Diamond and SiC IMPATT diodes also are capable of producing improved RF power compared to Si, GaAs, and InP devices at microwave frequencies. RF performance degrades with frequency and only marginal improvements are indicated at millimeter-wave frequencies. Bipolar transistors fabricated from wide bandgap material probably offer improved RF performance only at UHF and low microwave frequencies. >

Fundamentals of Solid State Electronics

Abstract: Electrons, bonds, bands and holes homogeneous semiconductor at equilibrium drift, diffusion, generation, recombination, trapping and tunneling metal-oxide-semiconductor capacitor P/N and other junction diodes metal-oxide-semiconductor and other field-effect transistors bipolar junction transistor and other bipolar transistor devices.

Applications of Quantum Semiconductor Structures

Abstract: This chapter discusses the applications of quantum semiconductor structures A new heterostructure type of FET has been developed that includes the two-dimensional electron gas field effect transistor also called high electron mobility transistor, modulation doped field effect transistor, or selectively doped heterojunction transistor depending on manufacturer It has features in common with both MESFETs and metal-oxide-silicon field effect transistors The structure is based on the heterojunction between AlGaAs and GaAs Its essential structure consists of a semi-insulating substrate on which is first grown a buffer layer of nonintentionally doped GaAs and on top of this is grown a thin layer of Al x Ga 1− x As, part of which is rather heavily n-type doped The gate metal forms a Schottky barrier to the AlGaAs and by making the ternary layer thin enough, the gate can completely deplete the AlGaAs layer of electrons Then the density of electrons on the GaAs side of the heterojunction is controlled by the voltage applied to the gate, so that the current between the source and the drain contacts can be controlled by the gate voltage

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Abstract: A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's

Abstract: Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible. >

Charge storage in a nitride‐oxide‐silicon medium by scanning capacitance microscopy

Abstract: In this paper we describe a variant of the scanning capacitance microscope (SCaM) which is based on the atomic force microscope. Our SCaM involves a cantilever beam that is used to press a conducting tip against a conducting substrate coated with a dielectric film. A capacitance sensor is then used to measure the tip‐sample capacitance as a function of lateral position. The deflection of the cantilever can also be used to measure independently the surface topography. This microscope can be used to measure electrical properties of dielectric films and their underlying substrates. We have applied this microscope to the study of the nitride‐oxide‐silicon (NOS) system. This system has been studied extensively because of its ability to store information by trapping charge in the silicon nitride. Commercial semiconductor nonvolatile memories have been designed using this NOS technology. We have used the SCaM tip to apply a localized bias to the NOS sample, causing charge to tunnel through the oxide layer and to...

Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS

Abstract: The authors demonstrate the feasibility of a p-channel quantum-well MOSFET on a Ge/sub x/Si/sub 1-x//Si heterostructure. The advantages of the enhancement-mode p-channel MOSFET device compared to GeSi MODFETs are its high impedance, channel mobility, and channel transconductance. The device shows good saturation and cutoff behaviour. A saturation transconductance of 64 mS/mm was measured for a 0.7- mu m channel device at a drain-to-source voltage of -2.5 V. The channel mobility was found to be higher than that of a similarly processed Si p-channel MOSFET. >

High-frequency equivalent circuit of GaAs FETs for large-signal applications

Abstract: The application of GaAs field effect transistors in digital circuits requires a valid description by an equivalent circuit at all possible gate and drain bias voltages for all frequencies from DC up to the gigahertz range. An equivalent circuit is presented which takes into account the gate current of positively biased transistors as well as the symmetrical nature of the devices at low drain voltages. A fast method of determining the elements of the equivalent circuit at all bias points without frequency limitations is presented. Direct computation from analytical expressions, without iteration, allows this parameter extraction procedure to be used for real-time on-wafer parameter extraction. Large-signal calculations are possible by inserting the voltage dependences evaluation for the elements into suitable simulation programs, such as SPICE. >

Thin-layer field-effect transistors with MIS structure whose insulator and semiconductor are made of organic materials

Abstract: A thin-layer field-effect transistor (TFT) with an MIS structure includes a thin semiconductor layer between a source and a drain. The thin semiconductor layer is in contact with one surface of a thin layer made of insulating material, and in contact by its other surface with a conducting grid. The semiconductor is composed of at least one polyconjugated organic compound with a specific molecular weight. The polyconjugated organic compound or polyconjugated organic compounds contain at least 8 conjugated bonds and have a molecular weight of no greater than approximately 2,000. The thin layer of insulating material is made of an insulating organic polymer having a dielectric constant of at least equal to 5. The transistor is useful as a switching or amplifying element.

High-gain lateral bipolar action in a MOSFET structure

Abstract: A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

Transcutaneous energy transfer device

Abstract: An improved transcutaneous energy transfer (TET) device comprises a primary winding for placement on or near a skin surface, and a secondary winding for implantation under said skin surface. A field effect transistor (FET) is arranged to switch said primary coil across an external DC power supply. A tuning capacitor is linked to said primary coil whereby said primary coil, when said FET is turned off, will resonate at its natural frequency thereby compensating for drift in component values and reducing power transfer sensitivity to component drift. In an alternative aspect of the invention, a bidirectional communications link is provided for the transfer of data across a boundary layer by infrared signals. A plurality of transmitters are arranged in a circular pattern on one side of the boundary layer, whereas a receiver is positioned within the circular pattern along the opposite side of the boundary layer.

Impact of the vertical SOI 'DELTA' structure on planar device technology

Abstract: A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance. >

Electric field effect in high Tc superconducting ultrathin YBa2Cu3O7−x films

Abstract: A multilayer high Tc superconducting field‐effect transistor‐like structure was made from ultrathin YBa2Cu3O7−x films. An epitaxially grown dielectric SrTiO3 insulation layer, which had a forward bias breakdown voltage of about 20 V, allowed an electric field induced change in the channel layer of 1.25×1013 carrier/cm2 per volt of the gate voltage. A significant modulation of the normal state and superconducting properties was observed in samples with YBa2Cu3O7−x channel layers of a few unit cells thick. By applying gate voltage of different polarities, Tc was both suppressed and enhanced by ∼1 K. The resistance was modulated by as much as 20% in the normal state and by over 1500% near the zero resistance temperature.

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Abstract: The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

Performance of thin hydrogenated amorphous silicon thin‐film transistors

Abstract: In this paper we have analyzed the influence of the mask channel length (LM) on the performance of the 55‐nm‐hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors (TFTs), incorporating nitrogen‐rich hydrogenated amorphous silicon nitride gate dielectric and phosphorus‐doped microcrystalline silicon (n+μc‐Si:H) source/drain (S/D) contacts. In our TFTs the n+μc‐Si:H S/D contacts have a specific contact resistance around or below 0.5 Ω cm2. We have shown that in our TFTs a field‐effect mobility and threshold voltage are dependent on LM, and this dependence is most likely due to the influence of the S/D contact series resistance on TFTs characteristics. Finally, we have demonstrated that if the mask channel length is extended by a ΔL (which is a distance from the S/D via edge at which the electron injection/collection is taking place) the field‐effect mobility and threshold voltage are independent of the channel length. In such a case μFE, VT, and ON/OFF current ratio around 0.76 cm2/V s, 2.5 V, and 1...

Power MOSFET transistor circuit with active clamp

Abstract: A power MOS transistor, including source, drain, and gate electrodes, comprises a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces; a drain region extending through the substrate between the surfaces; a plurality of spaced body regions of the opposite conductivity type extending into the substrate from the first surface; and a source region of the one conductivity type extending into the substrate from the first surface within each of the body regions, the interface of each of the source regions with its respective body region at the first surface being spaced from the interface of its respective body region and the drain region at the first surface to form a channel region therebetween. A gate electrode overlies and is insulated from the first surface and extends across the channel regions. A conductive electrode extends over and is insulated from the gate electrode, and contacts at least a portion of the source regions. A current limiting circuit is coupled between the conductive electrode and the gate electrode and a voltage limiting circuit is coupled between the drain electrode and the gate electrode.

An intelligent MOS transistor featuring gate-level weighted sum and threshold operations

Abstract: A novel functional MOS transistor which behaves much more intelligently than a mere switching device has been developed The device has a floating gate whose potential is controlled by a plural number of input gates via capacitive coupling The transistor is called a 'neuron MOSFET' due to its similarity to biological neurons in that the transistor turns on when the weighted sum of all input signals exceeds a certain threshold value Test devices were fabricated using a double-polysilicon NMOS process The analysis of the basic device operation and its experimental verification are presented A number of interesting applications of the neuron MOSFET are described which include a variable threshold transistor, a neuron circuit, a single-gate D/A (digital-to-analog) converter, and a soft hardware logic circuit >

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

Abstract: An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature. >

DRAM Cell with trench capacitor and vertical channel in substrate

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

Integrated charge pump circuit with back bias voltage reduction

Abstract: An integrated charge pump circuit with back bias voltage reduction includes one or more diode type voltage multiplier stages, with each stage having a diode-connected NMOS transistor in place of the conventionally-used p-n junction diode. The transistors are formed within a P-type well, which forms the back gate of each transistor within the well, and the transistor threshold voltages are dependent on the potential of the P-type well. Performance of the charge pump circuit using NMOS transistors is enhanced by the use of a bias circuit which generates a bias voltage as a function of the output voltage generated by the charge pump circuit, and applies this bias voltage to the P-type well to minimize the back-body effects of the NMOS transistors. The bias circuit thus permits the construction of an integrated charge pump circuit with significantly lower MOS diode voltage drops than would otherwise be possible.

Equivalent-circuit parameter extraction for cold GaAs MESFET's

Abstract: The physical basis of the cold-FET method for extracting parasitic resistances and inductances is examined. A method to obtain the source resistance from the gate-current dependence of the FET Z parameters is used to analyze FETs with different gate lengths. Inductance results for FETs with different gate widths suggest that inductance extrinsic to the gate fingers is dominant, and models of the gate inductance support this. The effects that possible dependences of the parasitic-FET equivalent-circuit parameters (ECPs) on the gate and drain bias can have on the extracted intrinsic-FET parameters are discussed. >

A graded channel field effect transistor

Abstract: A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transconductance of the device can be optimized by controlling the location of the carriers within the channel.

Extremely high gain 0.15 mu m gate-length InAlAs/InGaAs/InP HEMTs

Abstract: High electron mobility transistors (HEMTs) based on the InAlAs/InGaAs heterojunction grown lattice matched to InP were fabricated with 0.15 μm T-shaped gates. The use of an undoped InGaAs cap layer in the epitaxial structure leads to excellent gate characteristics and very high transistor gain. At 95 GHz, a maximum available gain of 13.6 dB was measured. A maximum frequency of oscillation fmax of 455 GHz was obtained by extrapolating from 95 GHz at –6 dB/octave. This is the best reported gain performance for any transistor.

A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process

Abstract: A floating-gate MOSFET which is programmable in both directions by Fowler-Nordheim tunneling and is fabricated using an inexpensive standard 2- mu m double-polysilicon CMOS technology is discussed. Tunneling occurs at a crossover of polysilicon 1 with polysilicon 2. Device layout and basic device characteristics are presented, and recommendations for efficient programming are given. This is the first floating-gate FET with a tunneling injector fabricated in standard technology that has close to symmetric programming characteristics for both charging and discharging of the gate. >

Thin film field effect transistor array for use in active matrix liquid crystal display

Abstract: A thin film field effect transistor array includes several parallel gate bus lines formed on a transparent insulative substrate, and several parallel drain bus lines formed on the transparent insulative substrate so as to intersect the gate bus lines. Several pixel electrodes are each formed in proximity of a corresponding one of intersections between the gate bus lines and the drain bus lines, and several thin film field effect transistors are each formed in proximity of a corresponding one of intersections between the gate bus lines and the drain bus lines. Each of the thin film field effect transistors is connected to a corresponding one of the pixel electrodes. Several of storage capacitors are each formed in proximity of and connected in parallel to a corresponding one of the pixel electrodes. Each of the storage capacitors is formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer. At least one of the first, second and third level capacitor electrodes is connected to a corresponding one of the gate bus lines.

Fermi threshold silicon-on-insulator field effect transistor

Abstract: A silicon-on-insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a Fermi Threshold SOI FET or Fermi SOI FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate channel doping. The vertical electric field in the substrate channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. The thin silicon layer in which the devices are formed is sufficiently thick such that the channel is not fully depleted at pinch-off. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Multiple gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.

Conductivity modulated MOSFET

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Process for fabricating a silicon on insulator field effect transistor

Abstract: A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).