Showing papers on "MOSFET published in 1990"

Silicon-on-insulator 'gate-all-around device'

Abstract: Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >

A physics-based MOSFET noise model for circuit simulators

Abstract: Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements. >

Integrated circuit device having improved junction connections

Abstract: A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon in to an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET

Abstract: A fully depleted lean-channel transistor (DELTA) that has a gate with a vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation is useful in realizing SOI isolation. It provides high crystalline quality, as good as that of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown that the gate structure has effective channel controllability and its vertical ultrathin SOI structure provides superior device characteristics. >

Subthreshold slope in thin-film SOI MOSFETs

Abstract: The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given. >

Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs

Abstract: Analytical models are proposed for thin- and ultra-thin film silicon-on-insulator (SOI) MOSFETs operating in weak or strong inversion. The models take into account all the device parameters. The cases of two and three interfaces with a silicon substrate are considered in the modeling and compared with one another. These models give the main electrical MOSFET parameters in ohmic operation (subthreshold swing and threshold voltage) for these structures. The basic approximation is the consideration of a linearly varying potential in the Si film, which has been inferred on the basis of numerical simulations. Various behaviors depending on the Si film and the buried insulator thickness as well as the interface charges, Si film doping, or substrate regime are simulated to assess the properties and the performances of SOI MOS transistors and to validate the analytical models. >

Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60-300 K

Abstract: Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q/sub b/, and inversion layer charge Q/sub i/. The experimental data for Q/sub b/ and Q/sub i/ were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) mu (E/sub eff/) dependence, which becomes more pronounced at low temperatures and low E/sub eff/, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures. >

Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's

Abstract: The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I/sub d/-V/sub g/ characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping. >

Characterization of carrier generation in enhancement-mode SOI MOSFET's

Abstract: The carrier generation in enhancement-mode SOI MOSFETs is studied by applying a suitable bias step on one gate, which drives it from depletion of accumulation to stronger accumulation and creates a deep-depletion condition under the other gate. An accurate analysis of this technique is made through a critical reexamination of the physical mechanisms and assumptions involved. By carefully considering all the essential events taking place in the device as it relaxes back to steady state, a Zerbst-type expression is obtained for the resulting current transients, which leads to a straightforward evaluation of the generation lifetime and surface generation velocity. The method is used to study SIMOX transistors, and it is shown that a very long lifetime can be achieved by multiple oxygen implants. >

The influence of the measurement setup on enhanced AC hot carrier degradation of MOSFETs

Abstract: It is shown that the enhanced degradation and substrate current component, which is observed in several AC experiments at the falling edge of the gate pulse under high drain bias, can in some cases be primarily ascribed to a carrier injection due to the forward biasing of the source diode and a simultaneous drain voltage overshoot. The forward biasing of the source diode is not caused by the commonly known latch-up effect, which is triggered by the substrate current, but by an insufficient AC coupling of the source to the ground due to the parasitic inductance of the wiring. It is demonstrated that by putting a capacitor at the drain side of the transistor and grounding the source at the probe tip, the observed enhanced substrate current can be eliminated and the anomalous enhanced degradation reduced accordingly. >

MOSFET multiplying circuit

Abstract: The invention relates to a voltage multiplying circuit having several stages, with each stage having a pumping capacitor and several MOS switching transistors. The switching transistors are so controlled by clock signals that the charge of a pumping capacitor of one stage is transferred to the pumping capacitor of the following stage. Operation of a circuit of this type with operating voltages substantially lower than 5 V entails considerable drawbacks. In accordance with the invention, therefore, each stage of a voltage multiplying circuit of this type is fitted with an additional transistor and an additional correction capacitor. As a result, the circuit in accordance with the invention is suppliable with an operating voltage of 2 V, for example. In another circuit arrangement, the transistors of the last two or three stages of the voltage multiplying circuit are of one conductivity type, while the transistors of the previous stages are of the opposite conductivity type. The last stages do not need a correction capacitor.

A self-aligned elevated source/drain MOSFET

Abstract: An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior. >

Thickness limitations of SiO/sub 2/ gate dielectrics for MOS ULSI

Abstract: The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si/sub 3/N/sub 4/ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current. >

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

Abstract: Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E/sub c/L/sub eff/, where E/sub c/ is the critical electric field necessary to cause carrier velocity saturation and L/sub eff/ is the effective channel length, is introduced. Experimental results confirmed that 1.1E/sub c/L/sub eff/ predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 mu m). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E/sub c/L/sub eff/ can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6- mu m channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E/sub c/L/sub eff/. >

Simulation studies of silicon electro‐optic waveguide devices

Abstract: Several silicon‐on‐insulator guided‐wave structures have been analyzed as potential electro‐optic waveguide modulators using the pisces‐ii two‐dimensional (2D) device simulation program. From the electron and hole concentration data, the 2D refractive index profile is obtained. The profile is then spatially averaged with respect to a 2D cosine representation of the guided‐wave E field to obtain the effective modal index changes at 1.3 and 1.55 μm. The channel‐waveguide devices studied include the metal‐oxide‐semiconductor (MOS) diode, and the one or two‐gate metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with single‐or double‐transverse injection. The single‐gate double‐injection MOSFET modulator offers the most promise with 10−3 refractive index changes possible, changes comparable in size to the Pockels effect in LiNbO3 or GaAs.

Luminescence spectra of an n‐channel metal‐oxide‐semiconductor field‐effect transistor at breakdown

Abstract: Photon emission occurs from the drain gate boundary of a metal‐oxide‐semiconductor field‐effect transistor when drain bias exceeds the drain‐to‐source breakdown value. Spectral measurement of luminescence has been carried out over a wide range 0.7–3.1 eV in order to understand the origin of the emission. Three different types of detectors are used to measure the luminescence spectrum. A continuous broad spectrum is observed with a peak near 1.0 eV. The emission intensity decreases almost exponentially in the higher energy range.

Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path

Abstract: A process for fabricating, on the more or less vertical edge of a silicon mesa, a MOS field-effect transistor which has a spacer-shaped gate and a right-angled channel path. The process involves the following steps: creating a raised region (the mesa) on a planar silicon substrate; creation of a gate oxide layer on the substrate and vertical sidewalls of the mesa; blanket deposition of a gate layer (typically polysilicon); anisotropically etching the gate layer to expose the upper surface of the mesa and leave a stringer gate around the circumference thereof; and doping the upper surface of the mesa and regions of the substrate peripheral to the circumferential polysilicon stringer to create source and drain regions. The standard process provides device density approximately double that of standard FET fabrication processes. Density can be increased even further by increasing the number of silicon mesas with a minimum pitch distance. This may be accomplished by employing the reduced-pitch masking technique disclosed in a copending U.S. patent application. Multiple transistors may be created on a single mesa by creating isolation regions within the mesa. The circumferential gate may be severed so as to provide a pair of gate inputs for transistors created on a single mesa. Enhancements common to conventional MOSFETS, such as lightly-doped source and drains, halos, etc., may be utilized for the new MOSFET process.

Dynamic input sampling switch for CDACS

Abstract: A low distortion capacitor sampling circuit includes a sampling MOSFET, the source electrode of which receives a time-varying input voltage to be sampled. A bootstrap capacitor has a first terminal connected to the gate electrode of the sampling MOSFET and to a first MOSFET that charges the first terminal of the bootstrap capacitor to a first voltage in response to a first control signal. A delayed second control signal is applied to the gate of a second MOSFET the drain electrode of which is connected to a second terminal of the bootstrap capacitor to keep the pulldown MOSFET on until the charging of the sampling capacitor is complete. Then a third control signal turns on a third MOSFET, boosting both terminals of the bootstrap capacitor. The second control signal then turns the third MOSFET off, electrically isolating the gate electrode of the sampling MOSFET. Changes in the time-varying input voltage are coupled by the gate-to-source capacitance of the sampling MOSFET to the gate electrode thereof. The input voltage is simultaneously applied to a source follower circuit, the output of which is coupled by a CMOS transmission gate to the body electrode of the sampling MOSFET. The circuit avoids harmonic distortion due to modulation of channel resistance of the sampling MOSFET by keeping the gate-to-source voltage and the source-to-body electrode voltage independent of the input voltage.

A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET for high current drivability and threshold voltage controllability

Abstract: A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET was investigated theoretically and experimentally Using an analytical model, it is verified that the mobility of the NUDC MOSFET is increased as compared with that of the conventional channel MOSFET Also, the V/sub th/ lowering of the NUDC MOSFET is suppressed as compared with that of the conventional channel MOSFET The NUDC MOSFET was fabricated by the oblique rotating ion implantation technique, and the theoretical predictions were confirmed experimentally >

Semiconductor structure with closely coupled substrate temperature sense element

Abstract: MOSFET devices (82) or circuits (80) incorporating an improved substrate temperature sensing element (94) are obtained by forming a PN junction (J2) directly on a thin (gate) dielectric region (140). The temperature sense junction (J2) is desirably formed in a poly layer( 134). By mounting it directly on thin (gate) dielectric (140) its thermal response to temperature changes in the substrate (111) is improved while still being electrically isolated from the substrate (111). It is desirable to provide over-voltage protection elements (100) coupled to the junction (J2) to avoid rupture of the underlying thin dielectric (140). Because the sense diode (94) and all the over-voltage protection devices (102) may be made of poly (136,138,144) with junctions (J2) perpendicular to the substrate (111), the structure is particularly compact and simple to fabricate.

Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate

Abstract: Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10). The buried wells (16a, 16b ) under the active areas (22a, 22b) have low resistance and enable the devices (52,54,58,62) to have high snap-back voltages. The absence of sharp edges also eliminates edge leakage upon high dosage irradiation, thus producing devices that are more radiation-resistant.

Scaling of digital BiCMOS circuits

Abstract: A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling. >

The effects of hot-electron degradation on analog MOSFET performance

Abstract: Many analog MOSFET performance parameters are found to be very sensitive to hot-electron stress, especially compared with digital parameters that are normally monitored Drain output resistance degradation is characterized in detail using existing hot-electron reliability concepts and lifetime prediction models The impact of drain output resistance degradation on the performance of a CMOS single-ended output differential amplifier is found to be a sensitive function of the particular circuit design and operating conditions >

Delay stage with reduced Vdd dependence

Abstract: A delay stage (60) has a delay period of reduced dependence on the level of a first voltage supply (Vdd). First and second inverter stages (78, 90) each have p-channel transistors (68, 86) and n-channel transistors (70, 88). The gates (64, 66) of the first inverter pair are connected to an input node (62). A fixed resistor (72) is inserted between the current path of the p-channel transistor (68) of the first inverter pair and a signal node (76). The current path of the n-channel transistor (66) of the first inverter is operable to connect the signal node (76) to ground. A MOSFET capacitor (80) is coupled to the signal node (76), as are the gates (82, 84) of the second inverter transistor (86, 88). The current path of the p-channel transistor (86) of the second inverter is operable to connect the voltage supply (Vdd) to an output node (92), and the current path of the n-channel transistor (88) of the second inverter (90) is operable to connect the output node (92) to ground. The trigger point of the second inverter stage (90) is chosen to be substantially the same as the difference between the voltage supply level and the threshold voltage of the transistor (86).

Semiconductor integrated circuit device

Abstract: PURPOSE:To reduce the generation of overshoot or undershoot and to attain high speed output signal by inserting a resistor between a source of an input element and a power supply line, and providing a switch element in parallel with a resistor. CONSTITUTION:A resistor R1 is inserted between a source of a P-channel output MOSFET Q1 and a power supply line Vcc, a resistor R2 is inserted between a source of an N-channel output MOSFET Q3 and a ground line and a P- channel MOSFET Q2 and an N-channel MOSFET Q4 are provided respectively in parallel with the resistors R1, R2. Then the FETs Q2, Q4 are subject to complementary switch control with an output MOSFET Q1 or Q3 with a proper delay time with respect to an input signal Di by an output signal Do. The switch MOSFETs Q2, Q4 are changed from the on-state into the off-state when the output signal in close to the ground level or power level and a resistor is inserted in series with the output MOSFET to reduce undershoot or overshoot and to attain high speed output signal.

2 kJ/s, 25 kV high frequency capacitor charging power supply using MOSFET switches

Abstract: A 2 kJ/s, 25 kV (Model CCDS-225) high frequency, capacitor charging power supply combining resonant technology and pulsewidth modulation has been developed. The power supply charges a capacitor to 25 kV at a rate of 2 kJ/s, and has a regulation of 90%. The HVPS is composed of the following modules: input power rectification and filtering, series resonant inverter, high-voltage transformer and rectification, control, and inverter drive. Using state-of-the-art MOSFET or IGBT (insulated-gate bipolar transistor) switches, the series resonant inverter operates at a frequency of approximately 50 kHz. The use of MOSFETs or IGBTs allows the HVPS to use a unique pulsewidth modulation control scheme for the resonant inverter. A proprietary control scheme and the 50 kHz resonant frequency makes it possible to achieve regulation better than 0.1% for load frequencies up to 2 kHz. In addition to superior regulation for high load frequencies, this unique control approach prevents the supply from being damaged if it is accidentally operated into an open circuit. The design of the power supply is described. >

Three dimensional devices fabricated by silicon epitaxial lateral overgrowth

Abstract: Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon over oxide are used for novel device technologies in CMOS and bipolar with a large potential for BICMOS. A stacked inverted P-MOS device in crystalline Si on top of an oxidized poly-gate was fabricated with the critical “as-grown” interface state densities, between the ELO silicon grown over the existing poly-oxide, measured to be less than 2 × 1011/ (cm2-eV) near midgap. A SiH2Cl2-HCl-H2 in a LPCVD epitaxial system was employed at 150 Torr and at 900° C to produce the ELO/SEG material. The initial stacked-inverted 3D P-MOS devices typically show hole mobilities of greater than 160 cm2/V-s with adequate subthreshold characteristics for 3-dimensional CMOS implementation. A new form of SEG was used to grow single crystal silicon horizontally between dielectric walls to form SOI material in thin slabs, called confined lateral selective epitaxial growth (CLSEG). BJT-SOI device structures with βdc > 150 were fabricated in CLSEG silicon to demonstrate the device quality material and to show the 3D-SOI capability.

A simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFETs

Abstract: A simple short-channel MOSFET model is proposed and applied to the delay analysis of CMOS inverters and series-connected MOSFET structures (SCMSs). The model is implemented in SPICE3 and shown to enhance the simulation speed. The model parameters for this model can be easily obtained. A delay analysis of the SCMS is carried out in the submicron region, and it is shown that the delay ratio ((delay of NAND/NOR)/(delay of inverter)) becomes smaller as channel length gets shorter. For example, if the maximum number of series-connected MOSFETS is considered to be five in 2- mu m designs, then the number can be increased to 6 approximately 7 in the submicron circuit design. In the typical cases in VLSI designs, the delay ratio for N-SCMSs is much less than N/sup 2/. >

Semiconductor device with photosensitivity

Abstract: A photosensor with improved performance is provided with a gate electrode structure for a field effect transistor that includes a semiconductor layer photosensitivity. The gate electrode can be constituted with a kind of metal or a low resistance semiconductor in conjunction with a semiconductor area with photosensitivity adjacent thereto. As a photosensitive semiconductor, amorphous silicon can be used because of its comparatively easy manufacturing method and its high sensitivity. As a field effect transistor, a thin film transistor of amorphous silicon can be used to correspond to the demand for making transistors over a large area. A MOSFET is preferably used as a field effect transistor for the improvement of sensitivity and speed of the sensor.

A universal MOSFET mobility degradation model for circuit simulation

Abstract: From the physical insights provided by the universal effective mobility versus effective vertical electric field curve for electrons in MOS inversion layers, a simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation. This expression is quite accurate over a wide range of channel doping concentrations and gate oxide thicknesses, without the need for fitting parameters, such as the theta parameter of the current SPICE level 3 mobility degradation model. It is, therefore, a much more universal model than the present SPICE level 3 mobility expression. Furthermore, the relative accuracy of this new model compared to the current SPICE model is expected to increase at the higher vertical electric fields typical of submicrometer oxide semiconductor field effect transistors (MOSFETs). >