Showing papers on "Tunnel field-effect transistor published in 2015"
TL;DR: This paper demonstrates band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on and is the only planar architecture tunnel-fET to achieve subthermionic subthreshold swing over four decades of drain current, and is also the only tunnel- FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts.
Abstract: A new type of device, the band-to-band tunnel transistor, which has atomically thin molybdenum disulfide as the active channel, operates in a fundamentally different way from a conventional silicon (MOSFET) transistor; it has turn-on characteristics and low-power operation that are better than those of state-of-the-art MOSFETs or any tunnelling transistor reported so far. Traditional transistor technology is fast approaching its fundamental limits, and two-dimensional semiconducting materials such as molybdenum disulfide (MoS2) are seen as possible replacements for silicon in a next generation of high-density, lower-power chip electronics. A particularly promising prospect is their potential in band-to-band tunnel transistors, which operate in a fundamentally different way from conventional silicon (MOSFET) transistors. So far, few such devices with overall characteristics better than silicon transistors have been demonstrated. Now Kaustav Banerjee et al. have built a tunnel transistor by making a vertical structure with atomically thin MoS2 as the active channel and germanium as the source electrode. It has turn-on characteristics and low-power operation that are better than those of existing silicon transistors, and the results will be of interest in a range of electronic applications including low-power integrated circuits, as well as ultra-sensitive bio sensors or gas sensors. The fast growth of information technology has been sustained by continuous scaling down of the silicon-based metal–oxide field-effect transistor. However, such technology faces two major challenges to further scaling. First, the device electrostatics (the ability of the transistor’s gate electrode to control its channel potential) are degraded when the channel length is decreased, using conventional bulk materials such as silicon as the channel. Recently, two-dimensional semiconducting materials1,2,3,4,5,6,7 have emerged as promising candidates to replace silicon, as they can maintain excellent device electrostatics even at much reduced channel lengths. The second, more severe, challenge is that the supply voltage can no longer be scaled down by the same factor as the transistor dimensions because of the fundamental thermionic limitation of the steepness of turn-on characteristics, or subthreshold swing8,9. To enable scaling to continue without a power penalty, a different transistor mechanism is required to obtain subthermionic subthreshold swing, such as band-to-band tunnelling10,11,12,13,14,15,16. Here we demonstrate band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on; subthreshold swing is a minimum of 3.9 millivolts per decade and an average of 31.1 millivolts per decade for four decades of drain current at room temperature. By using highly doped germanium as the source and atomically thin molybdenum disulfide as the channel, a vertical heterostructure is built with excellent electrostatics, a strain-free heterointerface, a low tunnelling barrier, and a large tunnelling area. Our atomically thin and layered semiconducting-channel tunnel-FET (ATLAS-TFET) is the only planar architecture tunnel-FET to achieve subthermionic subthreshold swing over four decades of drain current, as recommended in ref. 17, and is also the only tunnel-FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts. Our device is at present the thinnest-channel subthermionic transistor, and has the potential to open up new avenues for ultra-dense and low-power integrated circuits, as well as for ultra-sensitive biosensors and gas sensors18,19,20,21.
774 citations
TL;DR: In this paper, an extensive study is presented to describe the impact of partial hybridization on the device electrostatics and on current of a silicon dielectric-modulated tunnel field effect transistor (DM-TFET).
Abstract: An extensive study is presented to describe the impact of partial hybridization on the device electrostatics and on current of a silicon dielectric-modulated tunnel field effect transistor (DM-TFET). To gain insight into the various design considerations and factors influencing the sensitivity, both process-related issue such as cavity length variation and real-time issues related to biomolecules behavior such as partial hybridization, charge, and position of receptors/target molecules have been investigated through extensive numerical simulations. The results indicate that TFET-based sensor does not suffer from scaling issues and thus can help in miniaturization without compromising the sensitivity, unlike a nanogap-embedded DM-FET.
163 citations
TL;DR: In this article, a tunnel field effect transistor (TFET) based biosensor with a nanogap created by overlapping the gate on the drain side is proposed, where the maximum ratio of the drain current with absence and presence of biomolecules, which indicates the sensitivity, is as high as 10 10.
81 citations
TL;DR: In this paper, the authors proposed a dielectric engineered tunnel field effect transistor (DE-TFET) as a high-performance steep transistor, which is based on a homojunction channel and electrically doped contacts.
Abstract: The dielectric engineered tunnel field-effect transistor (DE-TFET) as a high-performance steep transistor is proposed. In this device, a combination of high- $k$ and low- $k$ dielectrics results in a high electric field at the tunnel junction. As a result, a record ON-current of $\sim 1000~\mu \text{A}/\mu \text{m}$ and a subthreshold swing (SS) below 20 mV/decade are predicted for WTe2 DE-TFET. The proposed TFET works based on a homojunction channel and electrically doped contacts both of which are immune to interface states, dopant fluctuations, and dopant states in the bandgap, which typically deteriorate the OFF-state performance and SS in the conventional TFETs.
71 citations
TL;DR: In this article, the dielectric engineered tunnel field effect transistor (DE-TFET) was proposed as a high performance steep transistor with high electric field at the tunnel junction, which achieved a record ON-current of about 1000 uA/um and a sub-threshold swing (SS) below 20mV/dec.
Abstract: The dielectric engineered tunnel field-effect transistor (DE-TFET) as a high performance steep transistor is proposed. In this device, a combination of high-k and low-k dielectrics results in a high electric field at the tunnel junction. As a result a record ON-current of about 1000 uA/um and a subthreshold swing (SS) below 20mV/dec are predicted for WTe2 DE-TFET. The proposed TFET works based on a homojunction channel and electrically doped contacts both of which are immune to interface states, dopant fluctuations, and dopant states in the band gap which typically deteriorate the OFF-state performance and SS in conventional TFETs.
69 citations
Abstract: We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd = 1 V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60 mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5 V.
58 citations
TL;DR: In this article, a hetero-junction fully depleted (FD) tunnel field effect transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed.
47 citations
TL;DR: In this paper, a novel architecture of tunnel field effect transistors (TFETs) with a circular gate is presented and the effect of electrical noise on the device by comparing the results with a hetero-junction TFET.
45 citations
TL;DR: In this article, a novel four-terminal ferroelectric tunnel field effect transistor (4T Fe-TFET) on SOI substrates where an extra tunnel-gate (T-Gate) isolated from the main drive gate has been placed over the source region of the TFET to achieve the steepest possible subthreshold swing (SS) characteristics below the Boltzmann limit.
Abstract: This letter reports a novel four-terminal ferroelectric tunnel field effect transistor (4T Fe-TFET) on SOI substrates where an extra tunnel-gate (T-Gate) isolated from the main drive gate has been placed over the source region of Fe-TFET to achieve the steepest possible subthreshold swing (SS) characteristics below the Boltzmann limit. The tunneling length of the Fe-TFET is observed to be decreased with the increase in the negative bias voltage of the T-gate which has been explored for improving the SS as low as 0.5 mV/dec for sub-30 nm channel length Fe-TFETs and thereby making the proposed 4 T Fe-TFET a wonderful quasi-ideal CMOS switching device.
40 citations
TL;DR: In this article, an analytical drain current model for gate dielectric engineered dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed.
Abstract: In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10−4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.
35 citations
TL;DR: In this paper, a 2D analytical model for the drain current of a dual material gate tunneling field-effect transistor is developed incorporating the effects of source and drain depletion regions, which is shown to be scalable down to a gate length of 50 nm.
Abstract: In this paper, a 2-D analytical model for the drain current of a dual material gate tunneling field-effect transistor is developed incorporating the effects of source and drain depletion regions. The model can forecast the effects of drain voltage, gate work function, oxide thickness, and silicon film thickness. The proposed model gives analytical expressions for the surface potential, electric field and the band to band generation rate which is numerically integrated to give the drain current. More importantly, our model accurately predicts the ambipolar current and the effects of drain voltage in the saturation region. A semi-empirical approach is used to model the transition from the linear to the saturation region, leading to an infinitely differentiable characteristics. The model is shown to be scalable down to a gate length of 50 nm. The model validation is carried out by a comparison with 2-D numerical simulations.
TL;DR: In this paper, dual metal-double gate tunnel field effect transistor (DMG-DGTFET) is discussed for mono and hetero dielectric gate material, and the results obtained from the simulation are discussed using energy band diagram, tunneling barrier width and compared with hetero & mono dielectoric gate.
Abstract: In this paper, dual metal-double gate tunnel field effect transistor (DMG-DGTFET) is discussed for mono & hetero dielectric gate material. The hetero dielectric that we have used at the gate is a combination of SiO$$_{\text{2 }}$$2 and HfO$$_{\text{2 }}$$2. The DMG technique is used to optimize the performance of DGTFET along with the mono/hetero dielectric gate material. The results obtained from the simulation are discussed using energy band diagram, tunneling barrier width and compared with hetero & mono dielectric gate. With the application of hetero dielectric to the DMG-DGTFET, the advantages of both the techniques combine and the results shows that higher $$I_{ON} /I_{OFF}$$ION/IOFF ratio $$(2\times 10^{9})$$(2×109) compared to the mono dielectric case $$(2.5\times 10^{8})$$(2.5×108). The average subthreshold slope also improves from 58 mV/decade in mono dielectric to 48 mV/decade in hetero dielectric DMG-DGTEFT. All the simulations are done in Synopsys TCAD for a channel length of 25 nm using the non-local tunneling model.
TL;DR: In this paper, the authors investigated the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor (JT-FET).
Abstract: For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope (< 60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
TL;DR: In this article, a detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported.
TL;DR: In this article, the authors presented improved device characteristics of a junctionless tunnel field effect transistor (JLTFET) with a Si and SiGe heterostructure for low power applications.
Abstract: In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure. Optimization of the device is done for low power applications. Heterojunction engineering is done to optimize the position of the Si:SiGe junction. Subsequently, band gap engineering is incorporated using variations in doping, gate work function, the mole fraction of SiGe and the dielectric constant. Comparison of the optimized, heterostructured silicon channel using numerical simulations indicates that ION increases from 0.12 to 15 μA μm−1, ION/IOFF increases from 4 × 106 to 3 × 109, and the subthreshold slope decreases from 80 to 43 mV dec−1 for a 22 nm channel with a supply voltage of 0.7 V.
TL;DR: In this article, the authors proposed analytical modeling of double gate (DG) tunnel field effect transistor (TFET) which is derived by using Evanescent-mode analysis approach, which considers the channel potential as the sum of a long channel potential and a short channel perturbation along with the whole structure rather than just the $$\hbox {Si}/\h box {SiO}_{2}$$Si/SiO2 interface or the channel centre.
Abstract: In this paper, we propose analytical modeling of double gate (DG) tunnel field effect transistor (TFET) which is derived by using Evanescent-mode analysis approach. This approach considers the channel potential as the sum of a long channel potential and a short channel perturbation along with the whole structure rather than just the $$\hbox {Si}/\hbox {SiO}_{2}$$Si/SiO2 interface or the channel centre. Due to this, the characteristic length lambda $$(\lambda )$$(?) does not depend on the transverse position within the channel. Analytical potential modeling of DG-TFET along with evaluation of electric field and drain current has been carried out. It has also been shown in the results that the proposed model has better channel potential and tunnel current than single-gate SOI TFET.
TL;DR: In this article, a heterojunction symmetric tunnel field effect transistor (S-TFET) was proposed and investigated, for the first time, in order to address the inborn technical challenges of the conventional p-i-n TFET (i.e., asymmetric TFET).
TL;DR: In this paper, the consequences of tunnel FETs' device characteristics, such as superlinear onset, uni-directional conduction, and dominant gate-drain capacitance, regarding the energy consumption, propagation delay, and noise resilience are investigated.
Abstract: This paper investigates the consequences of several distinctive device characteristics of tunnel FETs (TFET), namely super-linear onset, uni-directional conduction, and the dominant gate-drain capacitance, regarding the energy consumption, propagation delay, and noise resilience. Simulations have shown that these TFET specific characteristics have a detrimental effect on the dynamic response. We also report that their impact remains significant when operating voltage is scaled. Thus device level optimizations are required to eliminate these attributes to take full advantage of TFETs small subthreshold swing and low voltage operation.
TL;DR: In this paper, a technique of using a lightly doped source region, below the p-gate, was proposed to increase the barrier and prevent any leakage in junctionless tunnel field effect transistor (JLTFET).
Abstract: In this paper, we explain the problem of dramatic OFF-state leakage in junctionless tunnel field effect transistor (JLTFET) for a channel thickness greater than 10 nm. In JLTFET, with channel width greater than 10 nm, the depletion region primarily remains confined below the dielectric–semiconductor interface. Hence, we tend to incur significant leakage through the center of the device. With the help of 2D device simulations, we demonstrate that the cause of the leakage current is predominantly due to thermal injection in the source region and is concentrated through the center of the device. We suggest a technique of using a lightly doped source region, below the p-gate to increase the barrier and prevent any leakage. The proposed alteration records an improved I
ON/I
OFF ratio for JLTFET for a channel of width 20 nm.
TL;DR: In this paper, a CMOS process compatible p-channel tunnel field effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally.
Abstract: A CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current ( $I_{\mathrm{\scriptscriptstyle ON}}\sim 0.17~\mu \text{A}/\mu \text{m}$ at $\vert V_{G}\vert =0.5$ V after $V_{\mathrm {TH}}$ adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. $\sim 100$ mV/ decade up to 10 nA/ $\mu \text{m}$ ). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs.
Patent•
13 Mar 2015TL;DR: In this paper, a planar complementary metal-oxide semiconductor (CMOS) transistor was constructed on a single substrate, and a tunnel field effect transistor (TFET) was formed on the single substrate.
Abstract: An apparatus includes a structure that includes a single substrate, a planar complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate, a planar tunnel field-effect transistor (TFET) formed on the single substrate, and a mobility enhancement strength layer included in the planar CMOS transistor or included in the planar TFET
TL;DR: In this paper, the authors compared low-temperature microwave annealing (MWA) with high temperature rapid thermal anneal (RTA) of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field effect transistor (TFET).
Abstract: Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length ( $\lambda $ ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage ( $\mathrm{V}_{\mathrm {\mathbf {BTBT}}}$ ) indicates clearly that TFET annealed by MWA had a lower $\lambda $ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of $10^{\mathrm {\mathbf {8}}}$ , a low subthreshold swing, and an almost negligible drain-induced barrier lowering.
15 May 2015
TL;DR: This review has tried to cover various recently developed gate engineered TFET structures in terms of their current behavior to show that by cleverly engineering the gate electrode, TFETs with superior current characteristics can be realized.
Abstract: The gradual progress in the development of a Tunnel Field Effect transistor as a suitable alternative to conventional Metal Oxide Semiconductor Field Effect Transistor for achieving superior current performance in nanoscale low power device has been considered in this review. Beginning from a simple p-i-n reverse biased diode, we have tried to cover various recently developed gate engineered TFET structures in terms of their current behavior to show that by cleverly engineering the gate electrode, TFETs with superior current characteristics can be realized. Apart from this, we have also presented a concise discussion on the problem and possible solution of ambipolarity in TFETs, thereby making the use TFETs with low leakage current possible in complimentary digital circuits.
TL;DR: In this paper, the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field effect transistor (HG-EHBTFET) was investigated.
Abstract: We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of the inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher ION levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin s...
TL;DR: Design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed and the excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of the model.
Abstract: In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.
TL;DR: This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5 nm TF ETs.
TL;DR: In this article, the authors presented both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner, where 2D drain current model has been developed using initial and final tunneling length of band-to-band process.
Abstract: This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD sentaurus device simulation results.
TL;DR: In this article, a single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel.
Abstract: A single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel. The performance of the proposed device is assessed using 2-D simulations. We establish the prospect of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with: 1) low OFF-state current and low sub-threshold swing (SS) and 2) an ON-state current similar to that of a comparable single grain boundary poly-silicon thin film transistor (TFT). Our results indicate that the proposed single grain boundary dopingless PNPN TFET could be an ideal substitute for the conventional TFTs making it appropriate for low power display applications as well as the driver circuits.
TL;DR: In this article, the effects of variation in different structural parameters of a gate-on-germanium source (GoGeS) tunnel field effect transistor (TFET) on its electrical performance were investigated.
TL;DR: In this article, a GaSb/InAs junctionless tunnel FET is presented, which can be exploited as a digital switching device for sub-20 nm technology, at a low supply voltage of 0.4 V.
Abstract: We present a GaSb/InAs junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology. Numerical simulations resulted in an IOFF of ~8 × 10−17 A/μm, ION of ~9 μA/μm, ION/IOFF of ~1 × 1011, subthreshold slope of 9.33 mV/dec and DIBL of ~87 mV/V for GaSb/InAs JLTFET at a temperature of 300 K, gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.